DG MOSFET Research Articles

Symmetrical unified compact model of short-channel double-gate MOSFETs

An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickness Asymmetry

Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickness Asymmetry

TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET

In this paper, the effect of various device design engineerings such as channel engineering, i.e., graded channel (GC), gate stack (GS) engineering (high-κ), and dual-material gate (DMG) on double-gate MOSFET (DG MOSFET) have been analyzed using ATLAS device simulator. Furthermore, the combinations of these technologies i.e., GC, along with GS engineering, i.e., GCGSDG, and GS together with DMG, i.e., GS dual-material DG (GSDMDG), have been taken into consideration. The simulation results demonstrate that, out of the several design engineerings, the GCGSDG is the most suitable for high-speed switching applications. However, the GSDMDG provides superior performance as an amplifier.

New threshold voltage definition for undoped symmetrical DG MOSFET

A new threshold definition is proposed for symmetrical undoped double gate MOS (DGMOS). Threshold voltage is calculated using the potential model described in [1] with only two fitting parameters, the values of which do not depend on device geometry. Comparison with the results of numerical simulations and other models of V T is presented and good accuracy of the new model is demonstrated.

Computation Efficient Yet Accurate Surface Potential Based Analytic Model for Symmetric DG MOSFETs to Predict Current–Voltage Characteristics

A computation efficient yet accurate surface potentialbased analytic model for the symmetric double-gate MOSFETs is proposed to simulate double-gate device current-voltage characteristics in this paper. This model consists of a surface potential versus voltage input equation and a drain current expression, which are very similar to that proposed by J. R. Brews for the single-gate (SG) Bulk MOSFET. The model gets rid of requirement of the transcendent trigonometric function used in the previous model, thus, result in the computation efficiency. The model is also verified by extensive comparisons with rigorous numerical solutions under different operation conditions and geometry structures, thus, the new set of surface potential equation and drain current is the framework of a complete DG MOSFET model for computer-aided-design circuit purpose.

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm-3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

Analytical threshold voltage model for short-channel asymmetrical dual-gate material double-gate MOSFETs

For a symmetrical DG MOSFET with two different gate-metals with two work functions, ?m1 and ?m2, a threshold voltage model is derived and presented for different L1/L2 ratios. The solid lines correspond to the model results and the symbols to the simulation results. An analytical threshold voltage model in undoped short-channel DG MOSFETs with asymmetrical dual gate material is presented. The threshold voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. For verification of the model, the potential distribution along the channel length and the threshold voltage are compared with simulation results for a wide range of the device dimensions.

Large-Signal Model for Independent DG MOSFET

In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal-oxide-semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends.

An analytical study of undoped symmetric double gate MOSFET (SDG)

AbstractIn the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the Vds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.

Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain (AVO_OTA) along with three times higher cutoff frequency (fT_OTA) as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle (s/ σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 μA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology.

Threshold Voltage Control through Layer Doping of Double Gate MOSFETs

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an o therwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

Analytical low-frequency noise model in the linear region of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors

An analytical model for the transconductance to drain current ratio (gm/Id) of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors (DG MOSFETs) has been developed in the weak inversion and from linear to saturation region, using the conductive path potential approach. The obtained analytical model for gm/Id in the weak inversion has been extended in the strong inversion and in the linear region including the short-channel effects, as well as the surface roughness scattering, series resistance, and saturation velocity effects. The obtained gm/Id model from weak to strong inversion has been verified by comparing simulation and experimental results of DG MOSFET with gate length 50 nm and it has been implemented in modeling the 1/f low-frequency noise. The introduced noise model has been validated by developing a Verilog-A transistor noise model, which is in good agreement with the experimental noise results of DG MOSFET with gate length 50 nm in the linear region from weak to strong inversion.

Unified large and small signal non-quasi-static model for long channel symmetric DG MOSFET

We propose a unified model for large signal and small signal non-quasi-static analysis of long channel symmetric double gate MOSFET. The model is physics based and relies only on the very basic approximation needed for a charge-based model. It is based on the EKV formalism [Enz C, Vittoz EA. Charge based MOS transistor modeling. Wiley; 2006] and is valid in all regions of operation and thus suitable for RF circuit design. Proposed model is verified with professional numerical device simulator and excellent agreement is found.

Simulation of High–<I>κ</I> Dielectrics in Counter Doped Double Gate Metal Oxide Semiconductor Field Effect Transistors

With the continued scaling of the SiO 2 thickness below 2 nm in Double Gate MOSFET devices, a large direct-tunneling current flows between the gate electrode and silicon substrate is highly affecting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. The counter doped (p-type) Double Gate MOSFETs with high-κ gate dielectric material is modeled to obtain the transport characteristics, DIBL, I on /I off ratio, threshold voltage and subthreshold leakage current. Reduction of short channel effects are observed in counter doped (p-type) DG MOSFET with high-κ dielectrics. Drain induced barrier lowering (DIBL) is reduced to ≈25%, subthrehold leakage current is decreased to ≈50%, I on /I off ratio is increased to ≈75% and threshold voltage (V t ) is increased to ≈6% in 1 nm dielectric thickness T ox . Results show that counter doped DG MOSFETs with high-κ gate dielectric material is an effective method to reduce the short channel effects.

An approach based on particle swarm computation to study the nanoscale DG MOSFET-based circuits

The analytical modeling of nanoscale Double-Gate MOSFETs (DG) requires generally several necessary simplifying assumptions to lead to compact expressions of current-voltage characteristics for nanoscale CMOS circuits design. Further, progress in the development, design and optimization of nanoscale devices necessarily require new theory and modeling tools in order to improve the accuracy and the computational time of circuits' simulators. In this paper, we propose a new particle swarm strategy to study the nanoscale CMOS circuits. The latter is based on the 2-D numerical Non-Equilibrium Green's Function (NEGF) simulation and a new extended long channel DG MOSFET compact model. Good agreement between our results and numerical simulations has been found. The developed model can also be incorporated into the nano-CMOS circuits' simulators to study CMOS-based devices without impact on the computational time and data storage.

Effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs with continuous solution from accumulation to strong-inversion regions

In this work, the effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs are evaluated by an analytical method, and a global continuous channel potential solution, valid for a wide range of doping concentrations, is obtained by a single-piece potential equation with a good initial guess from the analysis. Extensive numerical simulations are performed to verify the proposed results. The study shows that the geometric parameter dependences of the threshold voltage in the doped transistors are ultimately different from that in the intrinsic ones, and the behavior of the channel center potential is also largely dependent on the body doping concentration. Moreover, the proposed channel potential solution is demonstrated to be not only accurate and continuous in the whole operation regime, but also valid for various doping concentrations and geometrical sizes of DG MOSFETs, without employing any fitting parameter.

Physics based capacitance modeling of short‐channel double‐gate MOSFETs

AbstractA precise compact 2D capacitance model for nanoscale DG MOSFETs in all operating regions is presented. The modeling of the sub‐threshold capacitances is based on the conformal mapping technique, where the corners of the device are treated specifically. In moderate to strong inversion, we obtain self‐consistent results based on the 2D Poisson's equation. The results are in excellent agreement with numerical simulations. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Fringe-induced barrier lowering (FIBL) included sub-threshold swing model for double-gate MOSFETs

A physical, compact, short-channel sub-threshold swing model for undoped-gate MOSFETs has been developed to include the fringe-induced barrier lowering effect associated with high-permittivity (high-κ) gate dielectrics. Using this new device model, we found that the degradation becomes worse when the channel length becomes shorter and both the off-state current (Ioff) and sub-threshold slope(s) rollup when κ is increased. It is indicated that a way to keep a reasonable channel length/vertical physical thickness ratio could be to suppress the FIBL effect in nanoscale DG MOSFET. The result showed that the analytical model was in agreement with the published numerical simulation over a wide range of device parameters.

A neural computation to study the scaling capability of the undoped DG MOSFET

The DG MOSFET is one of the most promising candidates for further CMOS scaling beyond the year of 2010. It will be scaled down to various degrees upon a wide range of system/circuit requirements (such as high-performance, low standby power and low operating power). The key electrical parameter of the DG MOSFET is the subthreshold swing (S). In this paper, we present the applicability of the artificial neural network for the study of the scaling capability of the undoped DG MOSFET. The latter is based on the development of a semi-analytical model of the subthreshold swing (S) using the Finite Elements Method (FEM). Our results are discussed in order to draw some useful information about the ULSI technology.

Advanced DG-MOSFETs Process Technologies

Double-gate (DG-) MOSFETs (DGFETs) have received much attention as promising silicon devices for future VLSI circuits thanks to their high short channel effects immunity. The innovative independent-double-gate four-terminal MOSFET (4T-DGFET) enables a new function of the threshold voltage controllability for the optimal power management. In this article, we present the recent progress in the fabrication processes of the fin-type DGFETs (FinFETs) and the 4T-FinFET with the separated double gates.