Fringe-induced barrier lowering (FIBL) included sub-threshold swing model for double-gate MOSFETs

Abstract

A physical, compact, short-channel sub-threshold swing model for undoped-gate MOSFETs has been developed to include the fringe-induced barrier lowering effect associated with high-permittivity (high-κ) gate dielectrics. Using this new device model, we found that the degradation becomes worse when the channel length becomes shorter and both the off-state current (Ioff) and sub-threshold slope(s) rollup when κ is increased. It is indicated that a way to keep a reasonable channel length/vertical physical thickness ratio could be to suppress the FIBL effect in nanoscale DG MOSFET. The result showed that the analytical model was in agreement with the published numerical simulation over a wide range of device parameters.