Abstract
The effect of fringe induced barrier lowering (FIBL) in Ge MOSFETs with high-k gate dielectrics is simulated with comparison to those of Si counterparts. It is observed that both Ge and Si devices undergo FIBL, which is dependent on gate length and permittivity of gate dielectrics. Germanium MOSFETs show less vulnerable FIBL effects than silicon counterparts in terms of DIBL and sub-threshold swing due to a higher permittivity in Ge. It is concluded that although FIBL cannot be eliminated, it will not be an issue if the gate relative permittivity used is small.
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