Abstract
A physical, compact, short-channel threshold voltage model for undoped double-gate MOSFETs has been extended through a phenomenological approach to include the fringe-induced barrier lowering (FIBL) effect associated with high-permittivity (high- k) gate dielectrics. The resulting analytical model closely describes published numerical simulations over a wide range of device/material parameters. Exploiting the new device model, a concerted analysis combining FIBL-enhanced short-channel effects and gate direct tunneling current is performed on candidate high- k gate dielectrics to assess their overall impact on DG MOSFET scaling. It is projected that high- k gate dielectrics may extend DG MOSFET scaling beyond that with SiO 2 by 10–20% for a 2–3× smaller equivalent oxide thickness of high- k dielectrics than that of SiO 2.
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