Delay Chain Research Articles

A Compact 1–11-GHz 106.7-ps CMOS Passive True Time Delay Chain Implemented by Spiral Transmission Lines

A Compact 1–11-GHz 106.7-ps CMOS Passive True Time Delay Chain Implemented by Spiral Transmission Lines

Design of a high-precision time-to-digital converter in an Elitestek Ti60 field-programmable-gate-array.

The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has garnered widespread attention due to its flexibility and high-performance capabilities. However, issues such as non-uniformity, the bubble in the tapped delay line, and the presence of certain ultra-wide delay units can significantly compromise the precision and nonlinearity of the TDC. In this paper, we propose a high-precision TDC in an Elitestek Ti60 FPGA, effectively eliminating the adverse effects of non-uniformity, the bubble, and certain ultra-wide delay units. The TDC is constructed with a 318-stage delay chain and operates at a low system clock frequency of 150MHz. The least significant bit (LSB) of the TDC is 21.92ps. The differential nonlinearity (DNL) is between (-0.976, 1.615) LSB and the integral nonlinearity (INL) is between (-1.446, 2.678) LSB. The TDC achieves a root-mean-square error of 14.783ps when utilized for measuring various time intervals.

50.3 ps time resolution and an 11-channel time measuring chip for Topmetal detectors

The Topmetal detector, utilized in this investigation, is a direct-type CMOS pixel sensor known for its distinctive feature of employing exposed metal at the top of each pixel to directly capture external charged particles. This method generates electrical signals through the induction of charge. At present, it is mainly used in gas pixel detector(GPD) and particle beam monitoring. In this paper, we present a new front-end design aimed at enhancing the capabilities of the Topmetal pixel detector. The focus is on incorporating a Time-Digital Conversion (TDC) ASIC into the front-end, with the objective of achieving high-precision time measurement in addition to superior position resolution. The function of the TDC is achieved by the two reverse delay chains, 11 edge acquisition circuits Time-to-Amplitude Converter (TAC), analog gate, weight count module, and Wilkinson Analog-to-Digital Converter (ADC). Coarse time measurement is implemented based on a counter with a working frequency of 500 MHz, and fine time measurement is implemented by the combination of TAC and ADC. The design prototype was taped out with the GSMCR130 nm technology. Test results show that this circuit can handle up to 11 consecutive cases, with the minimum time interval of adjacent cases being 500 ps and the bin size up to 2 ps. The time measurement precision is better than 50.3 ps RMS and the PVT(Process Voltage Temperature) robustness of the input delay chain circuit is validated, showing the stable performance of the design.

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

Project Schedule Delays and Associated Circular Impacts of Socio-Economic and Environmental Issues that can Affect Sustainability Footprint of Mega-Projects.

The Padma Multipurpose Bridge and the Dhaka Metro Rail mega-projects in Bangladesh have significantly influenced regional identity and culture. Both projects, with costs of US 2.8 billion respectively, experienced substantial schedule delays of up to 9 years. This study examines the socio-economic and environmental impacts of these delays, focusing on the circular effects they create. Circular effects refer to reinforcing feedback loops between socio-economic factors (such as employment, income, and displacement) and environmental factors (such as land use and resource depletion) that exacerbate delays and hinder sustainable development. A qualitative approach was employed, using a multiple case study design to ensure depth and context. Data were collected through semi-structured interviews with 20 engineers and 40 beneficiaries, selected via purposive sampling to represent diverse stakeholder perspectives. In addition, sentiment analysis was conducted on media reports to capture public perception of the project delays. The data were analyzed using thematic analysis, allowing for the identification of recurrent patterns, including the socio-economic and environmental impacts contributing to the delays. The analysis revealed seven key factors contributing to delays: inadequate project planning, frequent design changes, miscommunication among stakeholders, and lack of contractor engagement, among others. Each of these factors created a ripple effect, wherein socio-economic disruptions (such as job losses and reduced income) exacerbated environmental impacts (such as extended land use and resource depletion). This cycle, in turn, led to further project delays. Addressing these circular effects is essential for breaking the chain of delays and their compounding impacts on sustainability. Based on the findings, the study recommends the adoption of advanced technologies, the use of sustainable materials, and the implementation of robust project monitoring systems. These recommendations are grounded in the evidence collected, which showed that addressing the root causes of delays could significantly reduce both the socio-economic damage and the environmental footprint of mega-projects. By implementing these solutions, future projects can achieve more efficient timelines and promote sustainable development.

A high-precision frequency measurement method combining π-type delay chain and different frequency phase coincidence detection

A high-precision frequency measurement method combining π-type delay chain and different frequency phase coincidence detection

A 600 MHz-BW 154.3 dB-FoM current-mode continuous-time pipelined ADC in 12 nm CMOS

A current-mode two-stage continuous-time pipelined (CTP) ADC for wideband receivers is proposed in this paper, to eliminate power-hungry front-end trans-impedance amplifier (TIA). An improved current mirror with low input impedance and high linearity is used to receive the current input signal and duplicate it to the delay chain and the quantization path of the 3-bit first stage. Then, the residue current is amplified and filtered by an embedded 1st-order TIA and further quantized by the second stage, which is implemented by a VCO-based quantizer to improve ADC energy efficiency and anti-aliasing filtering. Simulation results in a 12 nm FinFET process show that clocked at 4.8 GS/s, the proposed ADC achieves 55.7 dB SNDR for a 600 MHz bandwidth and consumes only 83.4 mW power under supplies of 0.9 V, 1.2 V, and 1.5 V, corresponding to an excellent FoM of 154.3 dB.

CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack

Physical unclonable function (PUF) is a promising security-based primitive, which provides an extremely large number of responses for key generation and authentication applications. Various PUFs have been developed as central building blocks in cryptographic protocols and security architectures, however, the existing PUFs and their improvements are still vulnerable to modeling attacks (MA) with refined machine learning algorithms. In this article, a configurable butterfly delay chain-based PUF design framework is proposed to meet the requirements of randomness, reliability, uniqueness, and MA-resistance metrics. A configurable butterfly delay chain is introduced to create multiple pairs of symmetric paths and a strong PUF relying on the intrinsic delay fluctuations of two identical paths is built. Furthermore, a secure hash function is used to insert non-linearities into the PUF, and a BCH-based error correction algorithm is utilized to recover the actual responses under noisy environments. The proposed PUF is implemented on Xilinx FPGAs and three machine learning algorithms are used to evaluate the resistance against MA. Experimental results show that the randomness, reliability, and uniqueness of the proposed PUF are close to the ideal value (49.6%, 99.9%, and 49.9%, respectively), and the prediction accuracy reaches 50% that indicating a desirable resilient to MA.

A Picosecond Delay Generator Optimized by Layout and Routing Based on FPGA

A delay generator is a timing control device that can generate a delay for the input signal according to the actual requirements. A delay generator with a combination of rough delay and precise delay is implemented on a Xilinx Kintex-7 series FPGA with a design scheme based on carry delay chain. The delay generator uses the delay time parameters sent by the upper monitor to work and to reflect the current working state to the upper monitor. In this article, a theoretical model of the delay generator is designed, and a delay compensation scheme is proposed to make the working state of the theoretical model closer to the actual circuit. Through simulation experiments, the time resolution of the delay generator is 54 ps, and the time accuracy is less than 50 ps. The delay scheme adopted in this article is highly scalable, and the time resolution and time accuracy can be further improved. Finally, a theoretical model of the delay generator with relatively high time resolution is implemented through low resource occupancy rate and little workload.

DominoCIM: A 28nm 138.04TOPS/W Spike-Domain Computing-in-Memory 6T-SRAM Macro for AI and Embedded Applications

The realization of computing in memory based on SRAM(SRAM-CIM) can be divided into three domains: analog domain (AD-CIM), time domain (TD-CIM), and digital domain (DD-CIM). However, there exist corresponding disadvantages to the above methods. For AD-CIM, the calculation accuracy is poor. Moreover, the output stability of TD-CIM is limited. With a large overhead area, the layout and wiring of DD-CIM are complicated. Aiming to solve the shortcomings, this paper proposes a spike-domain circuit based on a pulse edge counting scheme. The circuit uses digital logic to realize the MAC operation, which is less affected by power, voltage, and temperature (PVT) and performs higher calculation accuracy. The circuit is transmitted serially through the delay chain to achieve a smaller area overhead. At 28 nm, the circuit accomplishes energy efficiency (EF) with 138.04TOPS/W for 4-bit multiplication and addition (MAC) operations, enabling full precision output and 3.42 times less energy consumption per operation than the previous SRAM-CIM.

All-digital transmit beamformer for portable high-frequency ultrasound imaging systems.

To meet the requirements of high-frequency ultrasound imaging systems, a transmit-beamforming integrated circuit with higher delay resolution than conventional transmit-beamforming circuits, which are typically implemented using field-programmable gate array chips, is presented. It also requires smaller volumes, allowing for portable applications. Its proposed design includes two all-digital delay-locked loops providing a specified digital control code for a counter-based beamforming delay chain (CBDC) to generate stable and suitable delays for exciting the array transducer elements without variations in process, voltage, and temperature. Moreover, to maintain the duty cycle of long propagation signals, this novel CBDC requires only a few delay cells, significantly reducing hardware costs and power consumption. Simulations were conducted, revealing a maximum time delay of 451.9ns with a time resolution of 652ps and a maximum lateral resolution error of 0.04mm at 6.8mm.

A dynamically reconfigurable entropy source circuit for high-throughput true random number generator

—True random number generator is an important hardware security primitive. Entropy source is the key to the design of a high-throughput true random number generator. To improve the throughput of a true random number generator while maintaining low hardware overhead, a novel entropy source circuit using ring oscillator with dynamically reconfigurable delay chain is proposed in this paper. The proposed entropy source exploits both signal jitter and circuit metastability. It consists of a seventh-order cycle shift register, seven 2-1MUXs and a core loop delay chain that is composed of inverters in series. Under the control of a high-frequency clock, the cycle shift register generates state transitions to control the output of MUXs, which in turn changes the number of inverters connected in the delay chain, switching the operation of the ring between steady and oscillating states. The outputs of five entropy sources are sampled and further XOR-ed with D flip-flops at a sampling clock of 400 MHz to obtain true random numbers. The proposed TRNG is implemented on the Xilinx Virtex-6 FPGA. The random numbers are captured in real-time using the Xilinx ChipScope and the TRNG is tested using the standard test specifications. The experimental results show that when working under a throughput of 400 Mbps, the proposed TRNG passes the NIST SP800-22 and the NIST SP800–90 B tests with a passing rate greater than 98% and a minimum entropy index per bit greater than 0.99. It also passes the relevant performance tests including autocorrelation test, restart test, deviation test, and temperature and voltage fluctuation test, and it has low hardware overhead.

Performance and Integration Results of a High Resolution Time-to-Digital Converter Designed for INO ICAL Experiment

INO ICAL Experiment emphasis on studying various properties of atmospheric neutrinos. A 50 kton Iron Calorimeter and Resistive plate Chamber (RPC) in stacked geometry will be used to track neutrinos. Position and directional information are to be used to identify particle energies. RPC detector signal of rise time less than 1ns is amplified-discriminated and given to Digital Front End (RPC-DAQ). To measure these fast pulses, we designed a low power, compact multi-channel Delay Chain based time-to-digital converter (TDC) in a 0.13μm CMOS process which will be integrated with the RPC-DAQ module. This TDC is capable of handling multiple hits per channel with a single-shot precision better than 65.34 ps. A 4-line or 11-line serial peripheral interface (SPI) is used for readout and configuration. This paper presents the performance and integration results of this TDC.

A 4.8ps root-mean-square resolution time-to-digital converter implemented in a 20nm Cyclone-10 GX field-programmable gate array.

It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement. In this study, we design a carry-look-ahead delay chain structure and integrate an interleaved sampling method with an online calibration and bin readjustment approach to implement a TDC. We take advantage of the adaptive logic module units applied in a Cyclone-10 GX (10CX220YF780E5G), which is a 20nm low-power consumption and low-cost FPGA. In this new generation FPGA, we implemented a high-precision time interval measurement, which exceeded all our previous works with a 4.8ps root-mean-square resolution and a 5.68ps least-significant-bit resolution.

DATIC: A Data-Aware Time-Domain Computing-in-Memory-Based CNN Processor With Dynamic Channel Skipping and Mapping

Due to the low-power priority of analog delay-based computation, time-domain computing-in-memory (TD-CIM) presents a splendid potential for energy-constrained edge and IoT scenarios deploying convolutional neural networks (CNNs). However, the latency in delay-based computation is proportional to the numbers and values of multiplications-and-accumulations (MACs), bottlenecking the throughput of previous data-agnostic TD-CIM-based processors which compute complete convolutions in a fixed MAC mapping manner. Firstly, some output activations in each layer of CNNs contribute less to the final classification results, which are insignificant and can be substituted by sums of partial MACs, with a marginal accuracy degradation. Thus, complete convolution computations lead to redundant MACs. Secondly, activations and weights vary with input images and models. Fixed MAC mapping leads to unbalanced MAC values on delay chains, causing long idle time and latency. To address that, we design a data-aware TD-CIM-based CNN processor, DATIC, with three techniques to reduce latency: 1) A channel-skipping TD-CIM macro to remove redundant MACs for insignificant output activations, by storing activations stationary in SRAM bitcells and shifting weights to perform only imperative MACs; 2) A convolution order programming unit to reduce overhead of skipping redundant MACs for insignificant output activations with random positions on feature maps; 3) An activation-weight-adaptive channel-mapping scheduler to balance latency of delay chains by dynamically altering convolution mapping manner. Implemented under TSMC 28-nm technology, DATIC achieves 622.9GOPS throughput and 32.7TOPS/W energy efficiency for ResNet-18 with 2-b weights and 8-b activations.

IECA: An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm² Area Efficiency

It remains challenging for a Convolutional Neural Network (CNN) accelerator to maintain high hardware utilization and low processing latency with restricted on-chip memory. This paper presents an In-Execution Configuration Accelerator (IECA) that realizes an efficient control scheme, exploring architectural data reuse, unified in-execution controlling, and pipelined latency hiding to minimize configuration overhead out of the computation scope. The proposed IECA achieves row-wise convolution with tiny distributed buffers and reduces the size of total on-chip memory by removing 40% of redundant memory storage with shared delay chains. By exploiting a reconfigurable Sequence Mapping Table (SMT) and Finite State Machine (FSM) control, the chip realizes cycle-accurate Processing Element (PE) control, automatic loop tiling and latency hiding without extra time slots for pre-configuration. Evaluated on AlexNet and VGG-16, the IECA retains over 97.3% PE utilization and over 95.6% memory access time hiding on average. The chip is designed and fabricated in a UMC 55-nm process running at a frequency of 250 MHz and achieves an area efficiency of 30.55 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.244 GOPS/KGE (kilo-gate-equivalent), which makes an over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.0\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.1\times $ </tex-math></inline-formula> improvement, respectively, compared with that of previous related works. Implementation of the IEC control scheme uses only a 0.55% area of the 2.75 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core.

A 19 μW, 50 kS/s, 0.008-400 V/s Cyclic Voltammetry Readout Interface With a Current Feedback Loop and On-Chip Pattern Generation.

A cyclic voltammetry electrochemical sensing chip was implemented with a time-based readout circuit and a current feedback control loop for wide-range and high-linearity current detection. The design utilizes a chopper-stabilized, low-noise potentiostat circuit and a delay chain time-to-digital converter to improve accuracy and the conversion rate. A current feedback loop is employed to mitigate nonlinearity of the current-to-frequency converter. Also, an on-chip pattern generator with a current reducer is used to create area-efficient, multi-rate ramp signals for cyclic voltammetry and fast-scan cyclic voltammetry measurements. The chip is fabricated using a 0.18-μm CMOS process. It achieves an 8-nA current resolution in the current range of -7 μA to 10 μA with an R2 linearity of 0.999 while consuming 19 μW. The Allan deviation floor is 4.83 Hz at the 7-second integration window, resulting in an 87-pArms input-referred current noise. The applicable limit of detection for K3[Fe(CN)6] concentration is 31 pM. To measure various reactions, the scan rate can be adjusted from 0.008 V/s to 400 V/s with a throughput data rate of up to 50 kS/s.

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL

This article presents a wide input-range delay chain based time amplifier (TA) and its application to a 6.5-GHz digital fractional- N phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma (ΔΣ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL's phase noise from DMRO flicker noise, which would otherwise degrade the PLL's in-band phase noise, and from ΔΣ FDC quantization error, which would otherwise degrade the PLL's phase noise at high bandwidth settings. This paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed ΔΣ FDC digital gain calibration technique. The TA-assisted PLL achieves a random jitter of 145 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , a total jitter that ranges from 151 to 270 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> as a result of fractional spurs, and a worst-case fractional spur of -49 dBc without requiring nonlinearity calibration.

2 ps Time-to-Digital Converter for Frequency Synthesis in 55 nm CMOS Technology

This paper presents a 2-ps time-to-digital converter (TDC) in 55 nm CMOS technology for all-digital phased-locked loop (ADPLL) system. Innovative inverter delay chain and Vernier delay chain cascade structure is adopted in the TDC to expand the measurement range while ensuring high resolution, so as to meet the wideband application requirements. Time window technology is employed to reduce circuit working frequency to save power by extracting single rising/falling edge of clock signal. Multiplexing technology is exploited to further reduce the power consumption by reusing the rising/falling edge detection delay chain of the first-level TDC, and also the time deviation detection circuit and resolution scaling factor detection circuit of the second-level TDC. The TDC features a differential nonlinearity (DNL) of 0.31 least significant bits (LSB) and an integral nonlinearity (INL) of 0.62 LSB, with a total current consumption of 4 mA from a 1.2 V supply voltage.

Digital Multiphase PWM Integrated Module Generated from a Single Synchronization Source

This article introduces a new architecture for a high-resolution digital pulsewidth modulator (HR-DPWM), which generates multiple output phases, all synchronized and derived out of a single reference source. Constructed through digital standard-cell delay chain and simple combinatorial logic, the module produces PWM signals with configurable on-time, period and time-delay (between phases) with resolution of a single delay element. To minimize the statistical error spread (e.g., jitter error) between phases, a single delay-line is utilized to generate a master time-base while combinatorial logic assigns per-phase independent duty-ratio settings. The resultant module minimizes the time-diversity error between phases, as any uncertainty in the on-time generation is identical between phases. The solution is compact, flexible and scales with the number of phases. Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described by HDL, which translates onto hardware using automated process. The HR-DPWM module has been designed and fabricated on a 0.18 μm 5 V CMOS process, totaling 0.08 mm2 of effective silicon area. Experimental results of a four phase 13-bit HR-DPWM are provided, demonstrating high accuracy and linearity characteristics with time resolution of 200 ps and excellent matching and tracking between all phases.