A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL

Abstract

This article presents a wide input-range delay chain based time amplifier (TA) and its application to a 6.5-GHz digital fractional- N phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma (ΔΣ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL's phase noise from DMRO flicker noise, which would otherwise degrade the PLL's in-band phase noise, and from ΔΣ FDC quantization error, which would otherwise degrade the PLL's phase noise at high bandwidth settings. This paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed ΔΣ FDC digital gain calibration technique. The TA-assisted PLL achieves a random jitter of 145 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , a total jitter that ranges from 151 to 270 fs <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> as a result of fractional spurs, and a worst-case fractional spur of -49 dBc without requiring nonlinearity calibration.