A 4.8ps root-mean-square resolution time-to-digital converter implemented in a 20nm Cyclone-10 GX field-programmable gate array.

Abstract

It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement. In this study, we design a carry-look-ahead delay chain structure and integrate an interleaved sampling method with an online calibration and bin readjustment approach to implement a TDC. We take advantage of the adaptive logic module units applied in a Cyclone-10 GX (10CX220YF780E5G), which is a 20nm low-power consumption and low-cost FPGA. In this new generation FPGA, we implemented a high-precision time interval measurement, which exceeded all our previous works with a 4.8ps root-mean-square resolution and a 5.68ps least-significant-bit resolution.