Delay Chain Research Articles

Phase modulation depth setting technique of a phase-generated-carrier under AOIM in fiber-optic interferometer with laser frequency modulation.

The phase modulation depth (PMD) in phase-generated-carrier demodulation is determined by the laser frequency modulation amplitude and working distance of a fiber-optic interferometer and must be set at a certain value. Active setting of the amplitude is unsuitable, especially for high-speed modulation, owing to variations in the laser source tuning coefficients. Existing calculation schemes for passive setting cannot work both owing to carrier phase delay (CPD) and the accompanied optical-intensity modulation (AOIM). Herein, a modified phase modulation depth calculation and setting technique is proposed. Double photoelectric detection and signal division are optimized to eliminate AOIM using a fiber delay chain and phase-locked amplifier module. Fast Fourier-transform and look-up table methods are used to calculate phase modulation depth without adding the carrier, which is unaffected by CPD. A fiber-optic Michelson interferometer is constructed to verify the feasibility of the proposed method. The experimental results show that AOIM can be eliminated; moreover, PMD can be calculated and set precisely. The displacement deviation is less than 1.03 nm. The resolution of measurement is considerably lesser than 1 nm and nanoscale accuracy is achieved in displacement measurement.

A 112 Gb/s PAM-4 RX Front-End With Unclocked Decision Feedback Equalizer

The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is investigated in this brief. Instead of clocked slicers and flip-flops, data-decision and feedback delay control are performed by saturated analog delay chains. As a result, the UC-DFE, previously exploited for NRZ signals, saves power consumption and silicon area while the simple implementation allows operation at high data-rate. A receiver front-end comprising a linear equalizer and the proposed 2-tap UC-DFE scheme is designed in 7 nm FinFET technology. From post-layout simulations, the receiver recovers a PAM-4 signal at 112 Gb/s after an 18 dB loss channel with a power efficiency of 0.47 pJ/bit. The receiver also works with NRZ signals at half the bit-rate equalizing 24 dB channel loss with a power efficiency of 0.70 pJ/bit.

Intelligent Prediction of Train Delay Changes and Propagation Using RVFLNs With Improved Transfer Learning and Ensemble Learning

In railway operation, train delays may occur due to various reasons (e.g. severe weather, infrastructure failure, human factors, etc.) and may change and spread rapidly to subsequent trains. Prediction of train delay changes and propagation is important to provide decision-making support for railway dispatchers to reschedule. In this paper, a multi-stage intelligent method is proposed for predicting the dynamic changes and propagation of train delays using random vector functional-link networks (RVFLNs) with improved transfer learning and ensemble learning. First, to improve the prediction performance of the single RVFLNs model, a novel improved Stacking ensemble learning RVFLNs (SRN) regression algorithm is proposed for prediction modeling of the delay changes. Then, to ensure the classification accuracy of unlabeled and class-imbalanced train data, an improved transfer learning RVFLNs (ITRN) classifier is proposed to decide whether the initial delay will lead to associated delays, with the aid of the improved SMOTE algorithm for processing imbalanced data. If associated delays are identified by the ITRN classifier, the proposed SRN algorithm will be further to predict the subsequent associated delays. By iterating the classification and prediction procedures, the propagation range and chain of train delays can be obtained. The effectiveness and practicability of the proposed method are verified by using two experiments against actual train graph data from different railway lines.

Detecting causality from time series in a machine learning framework.

Detecting causality from observational data is a challenging problem. Here, we propose a machine learning based causality approach, Reservoir Computing Causality (RCC), in order to systematically identify causal relationships between variables. We demonstrate that RCC is able to identify the causal direction, coupling delay, and causal chain relations from time series. Compared to a well-known phase space reconstruction based causality method, Extended Convergent Cross Mapping, RCC does not require the estimation of the embedding dimension and delay time. Moreover, RCC has three additional advantages: (i) robustness to noisy time series; (ii) computational efficiency; and (iii) seamless causal inference from high-dimensional data. We also illustrate the power of RCC in identifying remote causal interactions of high-dimensional systems and demonstrate its usability on a real-world example using atmospheric circulation data. Our results suggest that RCC can accurately detect causal relationships in complex systems.

A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems

This paper presents the design of a low power, compact multi-channel single-shot time-to-digital converter (TDC) capable of handling multiple hits per channel. The system has 17 hit channels and 1 trigger channel and is designed to meet the requirements of the iron calorimeter detector in the India-based neutrino observatory. The TDC core consists of a delay chain stabilized by a delay-locked loop (DLL) and synchronous counters. The digital backend is programmable to allow for multiple configurations during the operation. The common core to all channels with concurrent accessibility, choice of core clock frequency optimizing the trade-offs between performance, power and area, and optimal backend logic result in a compact and low power design. It achieves a single-shot precision better than 65ps. The 0.13 μm chip occupies an active area of 3.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 3.4 mW per channel. This paper also reviews the theory on how timing precision is defined for a single-shot TDC and explains how the test plan can be devised based on the jitter in the system.

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction.

This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.

A high precision TDC design based on FPGA+ARM

In this paper, a high precision time digital converter(TDC) is designed based on FPGA and ARM, It includes coarse module, delay chain module, look-up-table module, ringosc moduleand spi module in the FPGA chip. The ARM chip is used for reading the timestamp and printing through the serial port. The key technology of this design is using the CARRY4 block of Xilinx Aritex-7 series to construct a delay chain for finecount. The system clock is used as the coarse count. The timestamp is obtained by the combination of fine time and coarse time.In addition, the precison of TDC is improved by code density test. The experiment result shows that precision of TDC is 43.2ps.

High Precision CMOS Integrated Delay Chain for X-Ku Band Applications

A high-precision delay chain circuit integrated in a 0.18- $\mu \text{m}$ CMOS technology working in the frequency bandwidth of 8–18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay cell has larger delay-bandwidth product and is less prone to parasitic capacitances of inductor elements compared with conventional passive second-order APN delay cells. The fabricated chip utilizing the novel delay cell occupies an area of $0.9\times3.6$ mm2 and consumes 115.5- and 13.5-mW dc power from a 3.3-V voltage supply in its high- and low-power modes, respectively.

A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array.

A field-programmable-gate-array (FPGA) based time-to-digital-converter (TDC), which combines different types of delay chains in a single time measurement channel, is reported in this paper. A new TDC architecture is developed, and both a carry-chain and the DSP48E1 adders, which are integrated inside the FPGA chip, are employed to achieve high resolution time tagging. A single channel TDC has a 3.3 ps averaged bin size, a 5.4 ps single-shot precision, and a maximum sampling rate of 250 MSa/s. The differential-non-linearity of the single TDC channel is -3.3 ps/+24.1 ps, and the integral-non-linearity is within -10.4 ps/+68.6 ps. The TDC performance can be improved by using four TDC channels to measure one input signal, and a 3.4 ps single-shot precision can be obtained. Due to the implementation of the delicated TDC structure, only a small amount of digital resources is required to achieve the picosecond time measurement resolution. Therefore, the reported TDC architecture is suitable for multi-channel applications that require high time resolution measurements of multiple input signals.

A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7-$\mu$ m Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation

A video graphics array (VGA) (640 $\times $ 480) indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7- $\mu \text{m}$ global-shutter pixel in 65-nm back-side illumination (BSI) process. With a 4-tap pixel structure, we achieved motion artifact-free depth map. Peak current during exposure time has been reduced by current spreading with constant delay chain in the photo-gate driver. Column fixed-pattern phase noise (FPPN) from the constant delay chain is self-compensated by the proposed time-interleaving technique with the two inversely directional clock chains in the photo-gate driver. Quantum efficiency (QE) and demodulation contrast (DC) have been optimized by using appropriate optical engineering techniques with an optimal silicon thickness. As a result, QE of 34% at 940-nm near-infrared and high DC of 86% at 100-MHz modulation frequency have been achieved. In addition, motion artifact and column FPPN are successfully removed in the depth map. The proposed ToF sensor shows depth noise less than 0.57% with 940-nm illuminator over the working distance up to 4 m, and consumes only 160 mW for VGA output at 60 frames/s.

Delay Based Auto-Calibrated PVT Monitor System and Method

In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP’s (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.

CMOS integrated delay chain for X-Ku band applications

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 $$\upmu \hbox {m}$$ CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from 8 to 18 GHz. The fabricated chip occupies an area of $$1.2\times 2.7$$ mm$$^{2}$$ and has no DC power consumption.

A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector

A 77-GHz frequency-modulated continuous-wave (FMCW) generator is presented for millimeter-wave (mm-wave) radar applications. The FMCW chirp is provided by a mixed-mode phase-locked loop (PLL). A dual rising-edge fractional-phase detector based on time-to-digital converter (TDC) is proposed to overcome the problem caused by the rising and falling time mismatch. A 2.3 ns detection range, 10 ps resolution Vernier TDC is employed in the detector to cover the two consecutive rising edges with less power consumption. A self-calibrated delay chain is employed in the Vernier TDC to overcome process, voltage and temperature (PVT) variations. Furthermore, sampling-edge selection technique is utilized to avoid the glitch during phase detection. A divider-less frequency error estimator is presented to save area and power. By employing a coarse-fine segmented digital-to-analog converter (DAC), the generator supports triangular and sawtooth-like FMCW chirp with reconfigurable period and bandwidth. An LC voltage- controlled oscillator (VCO) with split varactor is proposed to improve the linear tuning range. Implemented in 65 nm CMOS, the FMCW generator consumes 99 mW power and 0.7 mm $\times $ 0.8 mm chip area. The measurement results show that the phase noise from 78.7 GHz carrier is −87.4-dBc/Hz at 1 MHz offset. The measured root-mean-square (RMS) frequency error of a sawtooth-like FMCW chirp with 4 GHz bandwidth and 0.1 ms period is 205 kHz.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Fine-time measurement circuit based on 180° phase-shifted clock sampling in time-to-digital converters.

Dead time is an important parameter in time-to-digital converters, which is the significant time measure circuit. To reduce the dead time, this note proposes a new fine-time measurement circuit. In this configuration, two clocks having a phase difference of 180° are used to sample the signals passing through the delay chain, and their average is taken as the final measurement result. The experimental results demonstrate that the dead time of the proposed circuit is observed to be 1.25 ns at 800 MHz clock and the circuit logic resource consumption of the proposed circuit is reduced by approximately 25% compared to other methods.

Nanoseconds Timing System Based on IEEE 1588 FPGA Implementation

Clock synchronization procedures are mandatory in most physical experiments where event fragments are readout by spatially dislocated sensors and must be glued together to reconstruct key parameters (e.g., energy and interaction vertex) of the process under investigation. These distributed data readout topologies rely on an accurate time information available at the front end, where the raw data are acquired and tagged with a precise timestamp prior to data buffering and central data collecting. This makes the network complexity and latency, between front-end and backend electronics, negligible within upper bounds imposed by the front-end data buffer capability where the raw data are stored waiting for the trigger validation. The proposed research work describes a field-programmable gate array (FPGA) implementation of IEEE 1588 Precision Time Protocol (PTP) that exploits the European Organization for Nuclear Research (CERN) timing, trigger, and control (TTC) system as a multicast messaging physical and data link layer. The hardware implementation extends the clock synchronization to the nanoseconds range, overcoming the typical accuracy limitations inferred by computers Ethernet-based local area network (LAN). Establishing a reliable communication between master and timing receiver nodes is essential in a message-based synchronization system. In the backend electronics, the serial data streams synchronization with the global clock domain is guaranteed by a hardware-based finite state machine that scans the bit period using a variable delay chain and finds the optimal sampling point. The validity of the proposed timing system has been proven in point-to-point data links as well as in star topology configurations over standard CAT-5e cables. The results achieved together with weaknesses and possible improvements are hereby detailed.

Design of a High Resolution TDC Based on Multi-channel

In this paper, a high precision time digital converter (TDC) system is designed based on Xilinx 7 series FPGA chip, which includes fine time measurement module, logic control module, rough count module and display module. The key point of FPGA TDC design is that there are a large number of delay units in the underlying hardware resources with stable delay. A delay chain consisting of 64 fast carry chains (CARRY4) is constructed by using the CARRY4 module inherent in the chip. In addition, the code density method is used to solve the nonlinear problem of internal special carry chain delay unit, effectively eliminate the error caused by wiring path, and reduce the integral nonlinear and differential nonlinear error. The experimental results show that the code density method can accurately reflect the distribution of delay time.

An On-Chip Digital Monostable Multivibrator Using Inverter-based Delay Chains

Monostable multivibrator or one-shot timer is widely used in signal processing. In this paper, a simple and useful way to realize retriggerable monostable multivibrator by using digital logic gates is presented. The basic circuit is composed of one D flip-flop, one NAND gate, one inverter (INV) and two inverter-based delay chains. The width of the output pulse is adjusted through tuning the delay of the inverter-based delay chain. The retriggerable characteristic is realized by resetting all the delayed signals when new triggering occurs in the current monostable period. The basic circuit is designed and fabricated on-chip using a 180[Formula: see text]nm standard CMOS process with effective area less than 1200[Formula: see text][Formula: see text]m2. The retriggerable version is realized in a FPGA platform. Both simulated and measured results are in agreement with the theoretical analysis.

A 125-ps 8–18-GHz CMOS Integrated Delay Circuit

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125- and 3.9-ps delay resolution, designed and fabricated in a 0.18- $\mu \text{m}$ CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second-, fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2–23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8–18 GHz. Input and output reflection coefficients are better than −11 dB for the delay chain including the effect of RF bondwires and pads. The fabricated chip occupies an area of $2.0\times 1.0$ mm2 and has no dc power consumption.

Study of low power front-ends for hybrid pixel detectors with sub-ns time tagging

Power consumption is always a concern in the design of readout chips for hybrid pixel detectors. The Timepix3 chip is capable of dealing with up to 80 Mhits/cm2/sec and tagging each hit within a time bin of 1.56 ns. At full speed the Timepix3 chip will consume 1.3 W. We consider how to reduce power consumption if hit rate and/or time stamp precision is not important. The analog power can be reduced by more than an order of magnitude with little impact on noise by reducing the bias current of the input transistor and increasing the return to zero time of the preamplifier. Digital power consumption might be ∼ 6× lower by reducing the clock frequency to 1 MHz from the nominal 40 MHz. Simulations and measurements are presented. In very low power mode Timepix3 could consume only ∼150 mW on 2 cm2. The new Timepix4 chip aims at time tagging within a bin of 200 psec. Propagation of a 5 GHz clock around the pixel matrix would be impractical. We present a novel architecture implementing a very low jitter clock to the full pixel matrix. A digital Delay Locked Loop is designed in which the delay chain is distributed along the two columns of each super-pixel with the phase comparator and control located at the base of the double column. The control system locks all super-pixels to the low jitter (<100 ps) global 40 MHz clock. Simulations show that this can be achieved with a power consumption of only 25 mW/cm2 while preserving high rate capability.