Abstract
In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP’s (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.
Highlights
With the increase of operation speed and area reduction of modern VLSI circuits, improved methodologies to allow circuits to operate at higher frequencies and improve power and timing management became an important area of study
It is assumed that the control system considers already how to respond depending on the delay levels, delay chain, and clock selection values provided by the PVT monitors
A PVT monitoring system and methodology that are intended to be used inside an IP were presented
Summary
With the increase of operation speed and area reduction of modern VLSI circuits, improved methodologies to allow circuits to operate at higher frequencies and improve power and timing management became an important area of study. A PVT detector presented in [20] senses the change of the PVT conditions using a delay line or delay chain (Figure 1) This delay line uses a logic inverter chain and D flip-flops (FF1, FF2). CK2 cells delay can cause a reduction in the granularity or range of the measurements This value will be captured and propagated to the Q1 output indicating that there is no detection of a high delay condition, equivalent to a non-significant PVT change. This monitor is using the same delay detector approach already explained, but using more flip-flops connected to different points of the delay line in order to detect different delay levels. Depending on the propagation delay of the delayed clock, and the setup time of a flip-flop, the Q output will be low or high, which can be expanded to detect different delay levels using more than one delay chain and multiple flip-flops
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