Abstract
The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods.
Highlights
IC (Integrated Circuit) designs must be verified in simulation for the expected range of operating conditions to ensure sufficient field [1]
Existing commercial timing analysis tools are mainly designed for nominal voltage to calculate cell delay with linear interpolation operation based on a two-dimensional library table, which may suffer from unacceptable accuracy loss at low voltages due to nonlinear characteristics
The reason for using HSPICE instead of PrimeTime to obtain the path delay is due to the lack of a timing library at low voltages, as well as the accuracy of the SPICE simulation, whose results were considered as the golden reference of the prediction initial solution, ft-1 (x) represents the (t-1)-th solution, ctj represents the weight coefficients, and T and J
Summary
IC (Integrated Circuit) designs must be verified in simulation for the expected range of operating conditions to ensure sufficient field [1]. With the rapid development of IC technology and the diversity of actual working situations, an increasing number of PVT (process–voltage–temperature) corners must be simulated at the same time to ensure the stability of chip operation. In [6], Michael et al used Gaussian process regression modeling to gradually iterate and expand the training set so as to obtain a subset of PVT corners with worst corners at the minimum simulation cost. In prior related learning-based timing analysis approaches, none focused on the issue of wide voltage design and no feasible way was provided to tackle the tradeoff between prediction error and simulation cost across supply voltage range. During the process of feature engineering, a dilated CNN (convolutional neural network) model is utilized to expand the feature dimensions by extracting the correlations among path delays for multiple PVT corners, which is beneficial to reduce characterization effort for each voltage node.
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