A dynamically reconfigurable entropy source circuit for high-throughput true random number generator

Abstract

—True random number generator is an important hardware security primitive. Entropy source is the key to the design of a high-throughput true random number generator. To improve the throughput of a true random number generator while maintaining low hardware overhead, a novel entropy source circuit using ring oscillator with dynamically reconfigurable delay chain is proposed in this paper. The proposed entropy source exploits both signal jitter and circuit metastability. It consists of a seventh-order cycle shift register, seven 2-1MUXs and a core loop delay chain that is composed of inverters in series. Under the control of a high-frequency clock, the cycle shift register generates state transitions to control the output of MUXs, which in turn changes the number of inverters connected in the delay chain, switching the operation of the ring between steady and oscillating states. The outputs of five entropy sources are sampled and further XOR-ed with D flip-flops at a sampling clock of 400 MHz to obtain true random numbers. The proposed TRNG is implemented on the Xilinx Virtex-6 FPGA. The random numbers are captured in real-time using the Xilinx ChipScope and the TRNG is tested using the standard test specifications. The experimental results show that when working under a throughput of 400 Mbps, the proposed TRNG passes the NIST SP800-22 and the NIST SP800–90 B tests with a passing rate greater than 98% and a minimum entropy index per bit greater than 0.99. It also passes the relevant performance tests including autocorrelation test, restart test, deviation test, and temperature and voltage fluctuation test, and it has low hardware overhead.