A 600 MHz-BW 154.3 dB-FoM current-mode continuous-time pipelined ADC in 12 nm CMOS

Abstract

A current-mode two-stage continuous-time pipelined (CTP) ADC for wideband receivers is proposed in this paper, to eliminate power-hungry front-end trans-impedance amplifier (TIA). An improved current mirror with low input impedance and high linearity is used to receive the current input signal and duplicate it to the delay chain and the quantization path of the 3-bit first stage. Then, the residue current is amplified and filtered by an embedded 1st-order TIA and further quantized by the second stage, which is implemented by a VCO-based quantizer to improve ADC energy efficiency and anti-aliasing filtering. Simulation results in a 12 nm FinFET process show that clocked at 4.8 GS/s, the proposed ADC achieves 55.7 dB SNDR for a 600 MHz bandwidth and consumes only 83.4 mW power under supplies of 0.9 V, 1.2 V, and 1.5 V, corresponding to an excellent FoM of 154.3 dB.