Cyclic ADC Research Articles

A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step.

A low power 10‐bit 1 MS/s cyclic analog to digital converter for complementary metal oxide semiconductors image sensors with comparator‐based switched‐capacitor technique

AbstractThis paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 W of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance.

Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter

This work presents the thermal noise analysis results of ring amplifiers in the MDAC of cyclic ADC. Ring amplifier is an alternative closed-loop structure for residual signal amplification with MDAC, and two types of ring amplifiers: pseudo-differential and fully-differential ring-amplifiers are considered for the implementation of MDAC in cyclic ADC. Theoretical analysis results show that power of thermal noise in MDAC with a pseudo-differential amplifier is much higher than that with a fully-differential ring-amplifier. SPICE simulation results with transient noise analyses also show the similar trend. Experimental prototype cyclic ADCs in 65nm CMOS technology are implemented with the same architecture and the same circuit components except for amplifiers. Comparison of the measured results of the two ADCs confirms the validity of the theoretical analysis results.

A low reference voltage interference 10-bit cyclic ADC based on current sub-DAC

A 10-bit cyclic ADC with current sub-DAC for column readout of CMOS image sensors (CIS) is presented in this paper. By charging and discharging sampling capacitors with current, reference voltages are static and stable, and thus the proposed cyclic ADC is suitable to be adopted in large-array readout circuit of CIS. The proposed cyclic ADC is designed in 0.11 μm 1-poly 4-metal CMOS technology. Large-array readout circuit of CIS based on the proposed cyclic ADC was simulated. According to the results of simulation, the proposed cyclic ADC under 3.3/1.5 V supply voltages achieves +0.30/-0.50 LSB maximum differential non-linearity (DNL), +0.80/-1.30 LSB maximum integral non-linearity (INL). It shows a 60.6 dB signal-to-noise and distortion ratio (SNDR) at 333 kS/s sample rate. Meanwhile, the proposed cyclic ADC can work stably at different process corners. The root mean square error (RMSE) of the transient positive reference voltage is 28 mV and it's 27 mV of the transient negative reference voltage. The proposed design effectively reduces the reference voltage fluctuation. Compared with the traditional 333 kS/s 10-bit cyclic ADC, the proposed one can reach the same analog to digital conversion accuracy and reduce power dissipation by 16%.

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental ΔΣ ( IΔΣ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ~3 better for 3D-stacked CIS. In addition, ramp and IΔΣ ADCs can both achieve (very) low fixed-pattern noise values.

Nonlinear error analysis and calibration model for cyclic ADCs in large array CMOS image sensors

A mathematical model is established to study the impact of nonlinear errors on the performance of cyclic analog-to-digital converters (ADCs) and imaging quality of CMOS image sensors (CIS). And a radix-based foreground digital calibration method for cyclic ADCs in large array CIS is proposed and modeled. The nonlinear errors caused by capacitor mismatch and finite operational amplifier (OPAMP) gain are mainly studied. Simulation results show that the proposed calibration method based on the statistical characteristics of large array CIS can effectively reduce the influence of nonlinear errors, greatly improve ADC linearity under large capacitor mismatch and finite OPAMP gain. In a CIS with 1500 columns of parallel ADCs, when the capacitor mismatch and OPAMP gain are 1% and 40 dB respectively, the effective number of bits (ENOB) of the calibrated ADC can be increased from about 6bit to 13bit. These results provide a new guideline for the calibration of cyclic ADCs in large array CMOS image sensors.

A low-power column-parallel cyclic ADC for CMOS image sensor with capacitance and current scaling

This paper presents a power-optimized column-parallel cyclic ADC for CMOS image sensor readout circuits. By separating the capacitor and bias current source and floating them in the circuit, the multiplying digital-to-analog converter (MDAC)'s capacitive load and bias current can be significantly decreased during least significant bit (LSB) quantization, which allows the ADC to reduce power consumption while maintaining a constant conversion rate. The residual quantization characteristic of MDAC makes the input-referred noise produced in LSB quantization relatively small, so the additional noise generated by capacitance scaling can be compensated by increasing the capacitance load of the most significant bit (MSB). A 14-bit two-stage column-parallel cyclic ADC is designed using 0.13-μm technology. The simulation results show that the effective-number-of-bit (ENOB) is 13.54 bit under 0.96-μs sampling rate, and the power consumption of each column is 631 μW. Compared with the traditional structure, the power consumption of ADC is reduced by 35.1%, while the performance remains unchanged.

Design of an 8‐bit time‐mode cyclic ADC based on macro modeling

SummaryThis work presents a macro modeling approach for the time‐mode cyclic ADC. The proposed ADC macro model is realized using the time‐to‐voltage converter (TVC) and the voltage‐to‐time converter (VTC) that are the key building blocks of time‐mode ADCs. In addition, the effect of circuit nonidealities and error sources of the time‐mode ADC including parasitic capacitance, current source output resistance, switch on‐resistance, capacitor mismatch, and comparator offset are incorporated in the macro model. The simulation time of the proposed ADC macro model showed 87.1% reduction compared to the all transistor level ADC circuit. As a result, the proposed ADC macro model can facilitate the ADC design and leverage the ADC nonideality analysis. Furthermore, the proposed macro model can be used for ADC calibration scheme development. As a practical design example, the macro model for an 8‐bit time‐mode cyclic ADC has been realized, where the nonideality analysis, design optimization, and calibration scheme development based on the proposed macro model have been demonstrated.

A Power Efficient Image Sensor Readout With On-Chip $\delta$ -Interpolation Using Reconfigurable ADC

In this paper, a low-power readout using reconfigurable cyclic ADC for CMOS image sensors is proposed. It reduces the total number of pixels to be read by taking advantage of pixel correlation. The required number of ADC operations is reduced, resulting in power saving. In contrast to the existing pixel correlation-based approaches, which focus only on the intensity differences, in the proposed method, the polarity of the differences is also taken into account. It helps in preserving fine edges representing features such as texture. The discarded or unread pixels are interpolated on-chip while reconfiguring the ADC input range according to the interpolation step size. Furthermore, this reduces the number of ADC conversion cycles by 25% to 50% for interpolation steps of 16 LSB and 64 LSBs, respectively. The ADC is designed and fabricated in UMC 180-nm CMOS technology, and the proposed method is verified for standard test images. The reconstructed images incorporating ADC non-linearities result in average Pratt’s FoM values of 0.88, 0.86, and 0.81 for 60%, 70%, and 74% compression, respectively. The corresponding best values achieved by the existing approaches are 0.86, 0.80, and 0.77, respectively. The improvement in FoM is observed due to the consideration of polarity information. The proposed technique results from 33% to 50% power saving for 80% compression in $512\times512$ image, using reconfigurable ADC. Therefore, it is suitable for a power efficient CMOS sensor design.

Design of a cyclic column-parallel ADC for Monolithic Active Pixel Sensor

This paper describes a 5-bit cyclic column-parallel ADC for Monolithic Active Pixel Sensor. The column-parallel ADC combines the dedicated sample phase and the signal conversion phase into a single phase. Moreover, it has a high tolerance to the offset of the comparators in the ADC by generating 1.5 bit in every stage. Each column-parallel ADC covers a small area of 100 μm × 200 μm, consumes 4.5 mW at 3.3 V supply and provides the sampling rate of 10 MS/s with the dynamic range of 1000 mV. The results show that the ADC has a signal-to-noise and distortion ratio (SNDR) of 28.47 dB. Its DNL and INL are −0.039/0.055 LSB and −0.048/0.095 LSB, respectively.

Inherently Accurate Attenuation-Based Digital Calibration of ADC

This paper presents inherently accurate digital calibration of ADC non-linearity, which requires neither absolute accuracy of a signal for calibration nor any modification of ADC core, hence enabling the use of existing ADC IP cores. It only relies on constant attenuation ratio provided by a passive resistive attenuator and hence it is inherently accurate as exemplified by extensive simulations as well as comparison with conventional method. A prototype $0.35\mu \text{m}$ -CMOS cyclic ADC with the on-chip signal generator for calibration has achieved the noise-limited 71.2-dB SNDR after the calibration under the sampling rate of 300 kS/s with 1.0-mW power and 0.087-mm2 chip area. The proposed calibration can be applied to the pipelined and cyclic ADCs with finite-gain non-linear op-amps as well as the SAR ADC.

A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC

A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/−0.5 LSB and +0.8/−0.9 LSB, respectively. The ADC consumes 435- $\mu \text{W}$ of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 $\mu \text{m}$ show that it is suitable for column-parallel readout in CMOS image sensors.

USER-SMILE: Ultrafast Stimulus Error Removal and Segmented Model Identification of Linearity Errors for ADC Built-in Self-Test

Linearity testing of analog-to-digital converters (ADCs) is very challenging and expensive due to the stringent linearity requirement on the stimulus and the extremely long test time. This paper introduces a novel method for ADC static linearity testing, allowing the stimulus linearity requirement to be significantly relaxed and the test time to be significantly reduced compared to the state-of-art histogram method. Two nonlinear but functionally related input signals are used as the ADC’s excitation and a stimulus error removal technique is used to recover test accuracy. With a segmented non-parametric integral nonlinearity model, this method requires much fewer parameters to accurately represent the nonlinearity. The proposed algorithm has been extensively verified and correlated in simulations. This method not only enables low-cost production testing but can also be used for low-cost on-chip built-in self-test. This method is limited to ADCs with segmented architecture such as SAR ADCs, pipeline ADCs, and cyclic ADCs.

Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC

This paper presents a prototype of 14 bit 80 kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redundancy of non-binary ADC tolerates the non-idealities of analog components such as capacitor mismatch and finite amplifier DC gain, the design consideration of this high accuracy ADC can be only focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier without any high accuracy analog components. The proposed proof-of-concept cyclic ADC has been designed and fabricated in TSMC 90 nm CMOS technology. Measured SNDR = 81.9 dB is achieved at Fs = 80 kSPS with a simple radix-value estimation technique. No other complicated digital calibration is used to compensate the non-linearity of ADC caused by MOM capacitors and a poor gain of the amplifier as low as 66 dB. Measured DNL is − 0.6/+ 0.67 LSB and INL is − 1.2/+ 1.6 LSB. Prototype ADC dissipates 8mW at supply voltage is 3.3 V in analog circuits.

A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components

A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components

Digital Calibration Technique for Cyclic ADC based on Digital-Domain Averaging of A/D Transfer Functions

Digital Calibration Technique for Cyclic ADC based on Digital-Domain Averaging of A/D Transfer Functions

3300万画素 120fps CMOSイメージセンサ用カラム並列2段サイクリック型ADCのデジタル補正の高精度・高速化手法

A digital calibration technique for a column-parallel two-stage single-ended cyclic ADC needs to accurately determine error coefficients that define the quantity of errors caused in the ADC. However, the error coefficients have so far been determined on the basis of estimation from the design parameters of the ADC. Therefore, we proposed a new ADC operation and signal processing scheme to determine them accurately and dynamically by measuring the ADC output code including the errors and verified its effectiveness for precise and high-speed technique of digital calibration by performing a preliminary experiment using the ADC test circuit.

A readout integrated circuit based on DBI-CTIA and cyclic ADC for MEMS-array-based focal plane**Project supported by by National Natural Science Foundation of China (No. 61271130), the Beijing Municipal Science and Tech Project (No. D13110100290000), the Tsinghua University Initiative Scientific Research Program (No. 20131089225), and the Shenzhen Science and Technology Development Fund (No. CXZZ20130322170740736).

A readout integrated circuit (ROIC) for a MEMS (microelectromechanical system)-array-based focal plane (MAFP) intended for imaging applications is presented. The ROIC incorporates current sources for diode detectors, scanners, timing sequence controllers, differential buffered injection-capacitive trans-impedance amplifier (DBI-CTIA) and 10-bit cyclic ADCs, and is integrated with MAFP using 3-D integration technology. A small-signal equivalent model is built to include thermal detectors into circuit simulations. The biasing current is optimized in terms of signal-to-noise ratio and power consumption. Layout design is tailored to fulfill the requirements of 3-D integration and to adapt to the size of MAFP elements, with not all but only the 2 bottom metal layers to complete nearly all the interconnections in DBI-CTIA and ADC in a 40 μm wide column. Experimental chips are designed and fabricated in a 0.35 μm CMOS mixed signal process, and verified in a code density test of which the results indicate a (0.29/−0.31) LSB differential nonlinearity (DNL) and a (0.61/−0.45) LSB integral nonlinearity (INL). Spectrum analysis shows that the effective number of bits (ENOB) is 9.09. The ROIC consumes 248 mW of power at most if not to cut off quiescent current paths when not needed.

A real-time digital calibration scheme for the cyclic ADC

A digital calibration scheme to correct the nonlinearity caused by finite amplifier gain and capacitor mismatch for the cyclic analog-to-digital converter (ADC) is presented. The calibration block of correcting the weight of the jumping points is implemented in which adders and registers are utilized without multipliers to reduce the silicon area cost. Each calibration block is shared by five ADCs. Ten switches are added into the 1.5-bit multiplying digital-to-analog converter to choose the test input signal and set the value of the most significant bit for measuring the heights of the jumping points. The capacitor mismatch and gain errors are measured as one error, and then the weight of the jumping points is compensated in the digital domain to improve the linearity of the ADC. Designed in a 0.18μm CMOS technology, the silicon area cost of each ADC is 0.03×1.7mm2 and the power consumption is 0.56mW at a supply voltage of 1.8V. The simulation results show that the calibration improves SNDR to 83.73dB from 55.13dB with 1% capacitance mismatch, and the calibration needs three conversion cycles which makes it real-time to obtain the changing error parameters during normal operation.

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

ABSTRACTThis article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m2.