Cyclic ADC Research Articles

Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal

High-precision analog-to-digital converter (ADC) testing is a challenging problem because of its stringent requirement on a test signal's linearity. This paper introduces a method that uses a nonlinear stimulus signal to test the linearity of high-resolution pipelined and cyclic ADCs by exploiting their architecture property. Simulation and experiments show that 16-bit ADCs can be tested to 1-LSB accuracy by using a 7-bit linear signal. This approach provides a solution to both the production and on-chip testing problems of high-resolution ADCs.

Digital Background-Calibration Algorithm for “Split ADC” Architecture

The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.

Capacitor-Swapping Cyclic A/D Conversion Techniques With Reduced Mismatch Sensitivity

This work proposes two capacitor-swapping techniques, random feedback-capacitor interchanging (RFCI) and averaging RFCI (ARFCI) techniques, for cyclic analog-to-digital converters (ADCs) to reduce the harmonic distortion caused by capacitor mismatch without trimming or calibration. The proposed RFCI and ARFCI techniques can be realized by simply rearranging the capacitor connections of the ADCs in different operation cycles. Hence, complicated circuits are not needed. The RFCI technique improves upon the spurious-free dynamic range (SFDR) of conventional ADCs without sacrificing the signal-to-noise-and-distortion ratio (SNDR). The ARFCI technique has better SNDR characteristics but less SFDR improvement than RFCI. With RFCI and ARFCI, the capacitor matching requirement is relaxed for high SFDR and the capacitance can then be reduced to meet the SNDR requirement, reducing the driving capability of the opamps, and thus reducing the total power and area of the ADCs. The prior commutated feedback-capacitor switching (CFCS) technique (see Yu , 1996) has less effect on the SFDR of cyclic ADCs but improves the signal-to-noise ratio (SNR). This work proposes a reconfigurable cyclic ADC architecture that can be easily reconfigured to operate with one of the RFCI, ARFCI, and CFCS techniques by a simple timing control circuit. This reconfigurable topology provides three conversion characteristics with one item of intellectual property (IP), rather than three separate IPs and thus greatly enhances the capabilities of cyclic ADCs.

A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB

A Wide Dynamic Range CMOS Image Sensor with Improved 12-bit Column Parallel Cyclic ADCs

We present very wide dynamic range (WDR) CMOS image sensor that integrates improved high-speed column-parallel cyclic ADCs.The proposed signal readout technique of extremely short accumulation (ESA) enables the dynamic range to be expanded to a very high illumination region.Including the ESA signals,a total of four different accumulation time signals are read out in one frame period using a burst readout technique.To achieve the high-speed and high-quality signal readout required for multiple exposure signals,column parallel high-speed A/D converters are integrated at the upper and lower sides of the pixel arrays.This improved cyclic ADC,with reduced random noise,better linearity and offset deviation,expands the dynamic range in the low illumination region.The resulting dynamic range is maximally dB.The improved 12-bit cyclic ADC has a differential non-linearity (DNL) of 0.3LSB.

CASIS1.0: A prototype VLSI front-end ASIC with ultra-large dynamic range and integrated ADC for silicon calorimetry in space experiments

In the framework of the INFN R&D project CASIS, a 6-channel prototype of an integrated front-end circuit optimized for silicon calorimeters to be used in future astroparticle physics experiments was designed and realized in a CMOS 0.35 μm technology. Five channels feature a double-gain charge sensitive preamplifier with real-time automatic gain selection, a correlated double sampling filter and, for test purposes, a fully differential, 12-bit cyclic ADC. A sixth channel, featuring only the ADC, is also implemented. The circuit design and test results are presented in this paper. The design goals of a linear dynamic range of 10 4 MIP (50 pC) in “low-gain” mode and a signal-to-noise ratio of 5:1 for single-MIP signals (with an input capacitive load of 300 pF) in “high-gain” mode were achieved.

A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters

A wide dynamic range CMOS image sensor with a burst readout multiple exposure method is proposed. In this method, maximally four different exposure-time signals are read out in one frame. To achieve the high-speed readout, a compact cyclic analog-to-digital converter (ADC) with noise canceling function is proposed and arrays of the cyclic ADCs are integrated at the column. A prototype wide dynamic range CMOS image sensor has been developed with 0.25-/spl mu/m 1-poly 4-metal CMOS image sensor technology. The dynamic range is expanded maximally by a factor of 1791 compared to the case of single exposure. The dynamic range is measured to be 19.8 bit or 119 dB. The 12-bit ADC integrated at the column of the CMOS image sensor has DNL of +0.2/-0.8 LSB.

Performance Analysis in General Cyclic ADCs

The cyclic A/D converting process is equivalent to iterations of a chaotic may using symbolic dynamics. The principle can be extended to construct "general cyclic ADCs" based on chaotic iterations. In this paper, the two necessary conditions of iterated maps are presented, and the new attributes of these converters are also discussed. By establishing a noise model, the analytic expressions of the random and system errors in general cyclic ADCs are derived and verified by simulations. With the same level of additive white noise, the optimal iterative maps for general cyclic ADCs are deduced.

Current-mode cyclic ADC for low power and high speed applications

A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements. >