Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

Abstract

This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental ΔΣ ( IΔΣ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ~3 better for 3D-stacked CIS. In addition, ramp and IΔΣ ADCs can both achieve (very) low fixed-pattern noise values.