A low reference voltage interference 10-bit cyclic ADC based on current sub-DAC

Abstract

A 10-bit cyclic ADC with current sub-DAC for column readout of CMOS image sensors (CIS) is presented in this paper. By charging and discharging sampling capacitors with current, reference voltages are static and stable, and thus the proposed cyclic ADC is suitable to be adopted in large-array readout circuit of CIS. The proposed cyclic ADC is designed in 0.11 μm 1-poly 4-metal CMOS technology. Large-array readout circuit of CIS based on the proposed cyclic ADC was simulated. According to the results of simulation, the proposed cyclic ADC under 3.3/1.5 V supply voltages achieves +0.30/-0.50 LSB maximum differential non-linearity (DNL), +0.80/-1.30 LSB maximum integral non-linearity (INL). It shows a 60.6 dB signal-to-noise and distortion ratio (SNDR) at 333 kS/s sample rate. Meanwhile, the proposed cyclic ADC can work stably at different process corners. The root mean square error (RMSE) of the transient positive reference voltage is 28 mV and it's 27 mV of the transient negative reference voltage. The proposed design effectively reduces the reference voltage fluctuation. Compared with the traditional 333 kS/s 10-bit cyclic ADC, the proposed one can reach the same analog to digital conversion accuracy and reduce power dissipation by 16%.