Abstract
Linearity testing of analog-to-digital converters (ADCs) is very challenging and expensive due to the stringent linearity requirement on the stimulus and the extremely long test time. This paper introduces a novel method for ADC static linearity testing, allowing the stimulus linearity requirement to be significantly relaxed and the test time to be significantly reduced compared to the state-of-art histogram method. Two nonlinear but functionally related input signals are used as the ADC’s excitation and a stimulus error removal technique is used to recover test accuracy. With a segmented non-parametric integral nonlinearity model, this method requires much fewer parameters to accurately represent the nonlinearity. The proposed algorithm has been extensively verified and correlated in simulations. This method not only enables low-cost production testing but can also be used for low-cost on-chip built-in self-test. This method is limited to ADCs with segmented architecture such as SAR ADCs, pipeline ADCs, and cyclic ADCs.
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