Counter Circuit Research Articles

Review Paper for SOC Estimation Techniques: Challenges and Future Areas for Improvement

This paper explores the advancements and challenges in State of Charge (SOC) estimation techniques for lithium-ion batteries, particularly within the context of electric vehicles (EVs) and renewable energy systems. As the global demand for sustainable energy solutions grows, accurate SOC estimation becomes essential for optimizing battery performance, enhancing safety, and extending battery life. The paper categorizes various SOC estimation methods into three primary approaches: direct measurement techniques, model-based methods, and data-driven algorithms. Direct measurement techniques, such as Coulomb counting and Open Circuit Voltage (OCV), are straightforward but often lack precision under dynamic conditions. Model-based methods, including Equivalent Circuit Models (ECM) and electrochemical models, provide detailed insights into battery behavior but can be computationally intensive. In contrast, data-driven approaches utilizing machine learning algorithms exhibit promising adaptability and accuracy, albeit relying heavily on large datasets. Despite these advancements, several limitations persist. Current SOC estimation methods are hindered by their dependence on accurate battery models and quality data, which can degrade over time. Furthermore, hybrid methods, which combine strengths from various techniques, introduce complexity and demand substantial computational resources. The integration of SOC estimation techniques in EV applications poses additional challenges due to varying operational conditions, necessitating efficient processing of real-time data from multiple sensors. Emerging trends in Battery Management Systems (BMS) are also examined, highlighting the role of AI and machine learning in improving real-time SOC computations and predictive capabilities. Cloud-based BMS systems are identified as a significant development for remote monitoring and control, enhancing the overall reliability of battery systems. This paper aims to provide a comprehensive overview of SOC estimation techniques, identify ongoing challenges, and suggest future research directions to enhance the effectiveness of battery management strategies in the evolving landscape of energy systems. DOI: https://doi.org/10.52783/pst.906

Energy efficient Wallace multiplier using symmetric stacking counter circuit

Multipliers show a dynamic part in numerous uses such as digital signal processing, filters and so on. Hence, the performance of the multiplier circuit has also to be improved more for better results. The circuit of the multiplier should be more compact and efficient to achieve the best outcome. Symmetric stacking counter circuit is designed using reversible logic gates and it reduces the power consumption. Various symmetric stacked counters are designed and used to implement the Wallace tree multiplier. The proposed multiplier is consumes 0.798mw of power and PDP of 2.47. The designed multiplier is power efficient as compared with existing methods with slight increase in delay. The proposed multiplier is used in low power application like modulators and demodulators.

Design of Ternary and Quaternary Asynchronous Up/Down Counter using CNTFET

This paper presents designs of ternary and quaternary up/down counters of single and multiple digits using CNTFET. The proposed counters have a special feature of counting in dual mode; up counting and down counting which makes these designs distinct from other existing designs. The proposed counters are designed using ternary/quaternary D flip-flops and a dynamic successor-predecessor circuit. The D flip-flops are built using standard ternary/quaternary inverters (STI/SQI) with an additional reset feature. The proposed dynamic successor-predecessor circuit has the capability of acting either as a successor or as a predecessor circuit based on a control signal. Counter circuits of multiple digits have been achieved with the help of a few additional transistors along with the single-digit counter circuits. All the proposed designs have been simulated in HSPICE using Stanford University’s 32 nm CNTFET model and simulation results have been noted. When compared with existing designs, the proposed designs show improvements in power and energy efficiency.

Design Of Electric Motorcycle Variable with Battery Management System

This study focuses on conceptualization and development of a battery management system (BMS) with two main functions, battery monitoring and management, in the context of brushless direct current motors (BLDCs). The main challenge in variable estimation is to protect the battery from potential risks during the charge and discharge cycle. The new proposed resolution combines a comprehensive BMS with monitoring capabilities for charge (SoC), health (SoH), voltage, current and battery temperature. In addition, a protective mechanism is incorporated to prevent variables from overshooting safety parameters. This research uses two different methodologies for estimating SOC, coulomb counting and open circuit voltage. In experimental tests, resistance potentiometers of 1,650, 3,300 and 0 were used, with SoC estimates of 37%, 19% and 65%, while coulomb counting method has a marginal error of 1.13%. On the contrary, the open-circuit voltage method generated a SoC estimate of 0% for all potentiometer resistance, with an error rate of 0.64 %. As a result, the open circuit voltage method is chosen because of its superior accuracy compared to the coulomb counting method. The state assessment of the battery showed a value of 100% after seven cycles. In addition, a protective system has been implemented to ensure that battery variables remain within the safe thresholds throughout the charge and discharge process. Consequently, the implementation of this BMS is expected to significantly improve overall performance and extend battery life.

Quantum Financial Modeling on Noisy Intermediate-Scale Quantum Hardware: Random Walks Using Approximate Quantum Counting

Quantum computers are expected to contribute more efficient and accurate ways of modeling economic processes. Quantum hardware is currently available at a relatively small scale, but effective algorithms are limited by the number of logic gates that can be used, before noise from gate inaccuracies tends to dominate results. Some theoretical algorithms that have been proposed and studied for years do not perform well yet on quantum hardware in practice. This encourages the development of suitable alternative algorithms that play similar roles in limited contexts. This paper implements this strategy in the case of quantum counting, which is used as a component for keeping track of position in a quantum walk, which is used as a model for simulating asset prices over time. We introduce quantum approximate counting circuits that use far fewer 2-qubit entangling gates than traditional quantum counting that relies on binary positional encoding. The robustness of these circuits to noise is demonstrated. While this paper is mainly about robust simplified quantum circuit designs, we compare some aspects of the results with price change distributions from stock indices, and compare the behavior of circuits with and without mid-measurement to trends in the housing market.

Faults Identification in Digital Counter Using Naïve-Bayes’ Algorithm

This paper elaborates on the implementation of the Naïve Bayes Algorithm to identify the faults occurrence in the digital counter circuits. The digital counters are circuits utilized to count the values in increasing order, decreasing order, or both directions. The digital counters find applications in real time from simple wristwatches to the industrial conveyor belt that is automated based on timings. The fault happening in the digital counter circuit is to be identified using Fault detection methods such as modular redundancy methods and error detection methods. With the advent of Artificial Intelligence algorithms, the identification of faults and errors in circuits is attained rapid manner. Though there are several machine learning algorithms such as Decision trees, Random Forest, K-Nearest Neighbor, and Support Vector Machines, the naïve Bayes algorithm is an easy and efficient algorithm to identify the errors in the circuits. This work concentrates on the naïve Bayes algorithm by developing the HDL code to predict the faults in the counter circuits. The proposed HDL code is validated for parameters namely power, area, and timing using the EDA tools.

Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design

The counters that change their transition using a clock signal are called synchronous counters. While designing a synchronous counter circuit, the power consumption and the delay are the major issues. Several synchronous counters were designed previously with the help of flip flops, but they did not provide good results. The existing synchronous counters increased power consumption and delay and decreased the speed. To overcome these issues, in this manuscript, a reversible synchronous counter is designed utilizing Multiple-Controlled Toffoli (MCT) and Multiple-Controlled Fredkin (MCF) reversible logic gates. Here, three JK flip-flop designs, such as JK1, JK2, and JK3 are designed for a reversible synchronous counter. Then JK1 and JK2 are structured by MCT. Whereas the JK3 flip-flop design is designed under MCF reversible logic gates. Coding is carried out Verilog, and then the proposed Reversible synchronous counter design (RSCD) is synthesized and implemented on FPGA using a Xilinx ISE 14.5 System generator. Here, performance metrics, such as delay, power, maximum counting rate, and total equivalent gate counts are examined. The efficiency of the proposed RSCD-MCT-MCF design attains gate counts of 23.45%, 28.94%, and 29.04% and is compared to the existing designs, such as Effective Designing of Reversible Synchronous Counters in Nanoscale (SCD-MTG), effective designing for reversible sequential circuits (SCD-3TG-4FG), designing of synchronous decimal counter utilizing reversible Toffoli–FredkinNetlist (SCD-TOF2).

Xilinx control circuit made to highlight injected fuel flow

The paper presents a control circuit made in Xilinx and which allows the adjustment of the frequency and the duty cycle of the control signal of an injector. The control circuit contains an oscillator and a selection circuit that provide specific commands to a counter. The oscillator that provides the clock frequency of a counting circuit uses the Nexis 4 DDR module’s own frequency. This is to be divided to the desired value by means of a divider implemented soft which makes changing the frequency easy. The signal obtained at its output commands a counter at which the maximum value of numbers is changed by a circuit selection. Thus, the variable duty cycle of the output signal of the development board is obtained, which is amplified both in voltage and in current, for compatibility with the injector parameters. The paper presents waveform obtained when resistive load operation as well as quantities of fuel injected in a given time interval.

Design of CNTFET-based Ternary Ring and Up–Down Counter Cells

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)’ unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits.

Design and Construction of a Modified SMS-Based Electronic Notice Board

This research aims to design and construct an electronic notice as an alternative to the traditional signpost parting on walls and billboards by providing practical, reliable and proper information dissemination. They consist of the following units, the power supply, voltage regulators, GSM modules, microcontroller, LED dot matrix display board, counter and subscriber identity module (SIM). The power supply comprises a 240/9 v ac 50 Hz step-down transformer rectifier filter and voltage regulations. AT89852, a low-power, high-performance CM05 8-bit microcontroller with 8 k bytes in-system programmable flash memory, is used in this design. A constant five v de is required to power microcontrollers and their associated input/output channel. GSM Modern is a wireless device that works with a GSM wireless network. The counter circuit of the device used to achieve this type of counting is the 5-stage Johnson decade counter. It is a typical chip in the 74HC555, with ten decoded outputs that go high one at a time. The assembler used for this research is MLAB version 5.7, downloaded from the microchip website. This window-based integrated development environment (IDE) software supports the PIC and other microcontrollers. The project constitutes both the software and hardware section for successful implementation. Operation more focus was given to the contribution of the system hardware. For verification of proper functionality of the message board, variation tests carry out and their results. Each component was carefully tested, and hardware troubleshooting and software debugging were carried out. The message was sent, and it appeared and started moving from left to right. In conclusion, by introducing the concept of wireless technology in communication, we can make our communication more efficient and faster with excellent efficiency, and the message can be displayed with less error and maintenance. This model can be used efficiently in establishments like colleges where in-order and special discounts can be displayed simultaneously at all branches. It is therefore recommended as a conventional model can say more than one message at a time LEDS have a limitation on size and a good number of characteristics. These can be replaced with large LED display boards, which not only catch bulb display attributes in a moving position one after another.

No calibration required two-step double-data-rate counter for low-power SS ADC in CMOS image sensors

This paper presents a low-power two-step double-data-rate (TS-DDR) counter without calibration for column-parallel single-slope analog-to-digital converter (SS ADC) in CMOS image sensor. A resolution alterable TS counting logic, which drives counting circuit to operate as a (N + M)-bit counter for the fine quantization and a M-bit MSB counter for the coarse quantization, is proposed to reduce the dynamic power consumption. As no calibration is required, the proposed counter is compatible with both digital correlated double sampling (D-CDS) and digital correlated multiple sampling (D-CMS). Moreover, a DDR structure without phase matching required for TS counter is employed to further reduce the power consumption. The proposed TS-DDR counter is implemented in 12-bit column-parallel SS ADCs for a CMOS image sensor. As a result, the proposed TS-DDR counter achieves a power consumption saving of at least 55.2% compared to a traditional one. The proposed SS ADC consumes 47.6 μW and has a DNL of +0.45/-0.55 LSB and an INL of +0.73/-2.36 LSB each column at 6.1 μs conversion time.

Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier

<span lang="EN-US">In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.</span>

High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit

High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit

A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process

This study investigated the use of a built-in-self-test (BIST) module detecting catastrophic errors in photon-counter accumulator for liquid contamination level measurement. Efficient algorithms are exceptionally demanded for a high-count rate and low voltage system photon counting circuit on-chip. The photon counter sensors are also required high sensitivity digital counter that encodes the arrival of photon in precise timing to prevent any count erroring the absence of light. The proposed BIST is integrated on the data acquisition system, where the accumulator is located. The design circuit, functionality and topology tests of BIST and circuit under test are realized with 180 nm Silterra CMOS Process. The same Verilog codes are verified using field programmable gate array (FPGA) to predict the hardware functionality prior fabrication. The measurement was able to detect at least 90 % fault coverage within 16-bit data acquisition system at minimum operating frequency of 166.7 MHz.

Design of Hybrid Counter using Adiabatic Quantum Flux Parametron

Power consumption is one of the most considered factors while designing any electronics digital circuit. In which, the Adiabatic Quantum Flux parametron (AQFP) is one of the best superconducting technology for reduced power factor. Adiabatic Quantum Flux Parametron (AQFP) will be powered by the use of AC (Alternating Current) in place of DC power supply. In this research article, a hybrid counter is designed based on Adiabatic Quantum Flux Parametron (AQFP). The hybrid counter is modelled using parallel counter circuits. This counter is designed based on different stages of manipulation. The different stages are based on the number of bits used in the design. Here the design is made up of 4 - bit hybrid counter with four stages of computation and due to these stages of computation, the computation cost is reduced up to 28% compared to existing semiconductor counter electronics circuits. Since the computation cost is reduced, which directly implies that the speed of design is high speed and power is also reduced in huge factors in range of nanowatts.

Grammatical Evolution of Complex Digital Circuits in SystemVerilog

The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit times 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit times 64-bit and 128-bit times 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit times N-bit multiplier. The Adder (6.4times), Multiplier (10.7times) and Selective Parity (6.7times) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog.

Observation of single photon interference and Hong-Ou-Mandel dip

We have built a cost effective Hong-Ou-Mandel (HOM) interferometer by using a conventional cheap multimode laser and a home-made coincidence counting circuit and we have observed the single photon interference and HOM dip making us to measure the bandpass filter. We expect it could be a good model to the graduates trying a variety of quantum optics experiments.

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

A Nearly Interference-Free and Depth-Resolution-Configurable Time-of-Flight System Based on a Mega-Pixel Vertical Avalanche Photodiodes CMOS Image Sensor

We present a long range (~250 m) time-of flight (TOF) system with suppressed (nearly-free) mutual-interference. The system is based on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1296\times960$ </tex-math></inline-formula> pixels vertical avalanche photodiodes (VAPD) CMOS image sensor (CIS). Real-time long-range 3D-imaging with 30 fps speed (450 fps for 2D imaging) is demonstrated. Designs and operation principles of the core circuits, i.e., a photon counting circuit and a global shutter driver, are fully described. The ranging method is based on a sub-range synthesis (SRS) where a range is set by the phase of exposure pulses with respect to that of the light source of the system. The depth resolution is configurable in that the minimum sub-range width limited by the light source pulse width of 10 ns or 1.5 m can be reduced to a 10 cm by introducing an indirect-TOF operation. Furthermore, by employing a random flight timing (RFT), mutual-interference in raw signal level is suppressed by 35 dB when 2 cameras are simultaneously operated. By simulation, the present system is estimated to be tolerant up to a case of 27 cameras operation.

Highly sensitive broadband photomultiplication type all-polymer photodetectors and their applications in optical pulse counting

Broadband photomultiplication type all-polymer photodetectors with the structure of ITO/PFN-Br/PBDB-T : PYF-T-o (3 : 100)/LiF/Au achieve EQEs of 18 000% at 360 nm and 9000% at 850 nm under 4 V, which are applied in an optical pulse counting circuit.