Abstract
The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit times 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit times 64-bit and 128-bit times 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit times N-bit multiplier. The Adder (6.4times), Multiplier (10.7times) and Selective Parity (6.7times) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog.
Highlights
Researchers began to explore the feasibility of the application of evolutionary algorithms (EAs) to circuit design tasks back in the early 1990s [2–4], which gave birth to the evolvable hardware (EHW) field
Based on results obtained, we conclude that the use of Grammatical Evolution (GE) and an hardware description language (HDL) (SystemVerilog) is capable of evolving complex combinational and sequential circuits, which answers the research questions set out in Sect
It should be noted that when comparing with state-of-the-art approaches, despite our evolved circuits requiring less gates to realize in silicon, the optimization of circuits evolved at an abstract level like register-transfer level (RTL) is largely dependent on the robustness of the synthesis tool
Summary
Researchers began to explore the feasibility of the application of evolutionary algorithms (EAs) to circuit design tasks back in the early 1990s [2–4], which gave birth to the evolvable hardware (EHW) field. EHW is made up two main sub domains: adaptive hardware and evolutionary design of conventional digital circuits [6]. The latter, adaptive hardware, refers to the continuous and autonomous reconfiguration or adaptation of evolved hardware to conform to changing operational requirements or conditions of its deployed environment over its lifespan [6, 7]. Sequential circuits on the other hand, are a class of circuits whose output(s) depends on both current and past input(s). The vast majority of circuits evolved in EHW literature are combinational This is partly due to complex circuit connections and unavailability of appropriate encoding structures for chromosomes that model feedback loops of sequential circuits [13]. In [26], CGP was modified to allow levels forward in order to model feedback loops of sequential circuits
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