Chapter 9 - HDL-Based Design Flows

Abstract

This chapter discusses the development of design tools and flows based on the use of hardware description languages (HDL). The chapter focuses on the use of a generic digital HDL as part of a design flow and introduces some of the popular digital HDLs. The functionality of a digital circuit is represented at different levels of abstraction and different HDLs support these levels of abstraction to a greater or lesser extent. The lowest level of abstraction for a digital HDL is the switch level that refers to the ability to describe the circuit as a netlist of transistor switches. A slightly higher level of abstraction is the gate level that refers to the ability to describe the circuit as a netlist of primitive logic gates and functions. The key feature of HDL-based application-specific integrated circuits (ASIC) design flows is their use of logic synthesis technology. The logic synthesis application automatically converted the register-transfer level (RTL) representation into a mixture of registers and Boolean equations and generated a gate-level netlist that meet the original timing constraints.