Chapter 7 - FPGA Versus ASIC Design Styles

Abstract

This chapter provides an overview on some of the significant differences between application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) design styles. When it comes to the language-driven design flows, ASIC designers tend to write very portable code (in VHDL or Verilog) and to make the minimum use of instantiated (specifically named) cells. By comparison, FPGA designers are more likely to instantiate specific low-level cell. Furthermore, pure FPGA users tend to use far more technology-specific attributes with regard to their synthesis engine than do their ASIC counterparts. Moreover, in order to bring up (or maintain) performance, FPGA designs tend to be more highly pipelined than their ASIC counterparts. This is facilitated by the fact that every FPGA logic cell tends to comprise both a look-up table (LUT) and a register that makes registering the output very easy. Depending on the task, ASIC engineers may include asynchronous structures in their designs where these constructs rely on the relative propagation delays of signals to function correctly. These techniques do not work in the FPGA world as the routing (and associated delays) can change dramatically with each new run of the place-and-route engines.