Chapter 3 - Optimizing the Development Cycle

Abstract

This chapter focuses on optimizing the development cycle. Most successful field-programmable gate arrays (FPGA) design teams follow a defined design flow. The order and relationships among the required design steps are fixed for most projects. The highest level of the FPGA design flow starts with design specification and follows through to volume product manufacturing. To develop a system rapidly and efficiently, it is essential that an optimized design flow be adopted and then followed. This optimized design flow should help the design team remain focused on implementing the design tasks in the most efficient sequence possible. The optimized design flow should also highlight critical design decisions and encourage extra diligence when making these decisions. The FPGA design flow is inherently iterative in nature. Many design decisions will have significant influence on the efficiency of subsequent design stages, including FPGA family, device, language, tool, and design hierarchy selections. The primary objective in rapid development is to shorten the design cycle—the cycle from the definition of system requirements to the demonstration of working functionality. This can be best accomplished by limiting/reducing the conventional iterative nature of the FPGA based design cycle. The high-level design phases associated with FPGA design include requirements, architecture and design, implementation, and verification. The design team should develop and maintain a detailed functional specification taking into account potential design enhancements and modifications. The design team ideally will maintain the flexibility of the FPGA design throughout the design cycle. This will increase the range of options available to the design team.