Chapter 9 - Design Constraints and Optimization

Abstract

This chapter focuses on design constraints and optimization. Constraints are used to influence the field-programmable gate arrays (FPGA) design implementation tools, including the synthesizer and place-and-route tools. They allow the design team to specify the design performance requirements and guide the tools toward meeting those requirements. The implementation tools prioritize their actions based on the optimization levels of synthesis, specified timing, the assignment of pins, and the grouping of logic provided to the tools by the design team. The four primary types of constraints include synthesis, input/output (I/O), timing, and area/location constraints. One of the most important constraint implementation issues is the overlapping and interference of the wide range of potential configuration. The effective design constraint implementation requires a solid knowledge and understanding of both the system requirements and the current design implementation approach. It is critical that clock assignments be verified and double-checked against all available clock-related documentation. Area constraints define a potential placement region for design elements. The process of laying out multiple design element blocks onto the target FPGA architecture is commonly referred to as “floorplanning.” A functional implementation example illustrated in the chapter demonstrates the relationships among the different design constraint categories. The optimization of FPGA design can be a challenging design phase. There are many different approaches requiring different levels of effort. The order in which optimization efforts occur is important because some optimization activities can affect the results of previously applied efforts. Following an established optimization procedure can help make the optimization phase more efficient.