Chapter 13 - Cores and Intellectual Property

Abstract

This chapter discusses some of the trade-offs, decisions, and design team actions that must be completed by the design team to implement design functionality with intellectual property (IP) blocks. FPGA intellectual property (IP) can be defined as a reusable design block with a fixed-range of functionality. The term “IP” usually refers to a preverified functional design block that is obtained from a group outside the local design team. There are three commonly recognized types of IP: soft IP, firm IP, and hard IP. It is important to realize that the definitions of IP may be different within the fields of application-specific integrated circuit (ASIC), standard cell, and software design. The hard IP is an optimized, fixed-function implementation at the silicon level. Firm cores imply some level of architecture awareness, specifying a combination of physical placement interrelationship, design element placement, and physical signal routing. Because soft cores have typically not been optimized for specific device architecture, the implementation of the functionality may not be optimally placed. Soft and firm cores, because of their programmable implementation, are inherently flexible with variability in their portability based on the way they are implemented. The range of IP availability can be divided into broad, overlapping categories that are differentiated by their application or functionality: processing, specialty, and interface. The IP trade-off analysis can be a challenging undertaking mainly because of the numerous available IP options. The integration of IP functionality can be a significant percentage of the effort required to implement IP within a design. It is advisable to verify the functional performance of an IP block once it has been implemented within a design. IP elements can provide significant risk reduction and schedule reduction for projects—with fast time-to-market requirements—and teams—with limited resources or specialized experience.