Chapter 6 - Board-Level Design Decisions and Allocation

Abstract

This chapter discusses design details associated with field-programmable gate arrays (FPGAs) that affect board-level design and implementation decisions. FPGA devices differ significantly from the majority of fixed function, fixed I/O devices mounted onto a printed circuit board (PCB). The two most common FPGA package types are quad-flat packs (QFPs) and ball-grid arrays (BGAs). BGAs have the advantage that the linear contact-to-contact (ball) separation is larger than the linear pin-to-pin separation of the traditional fine-pitch QFPs. This reduces solder bridging but at the cost of a more complex, automated assembly process. This is fine for high volume production. Even when signal assignment is made carefully and based on a combined, informed, and detailed board-level and FPGA-level signal flow mode that takes into account all signal interfaces, some changes and updates are required. A power analysis of PCB device may indicate that there are thermal issues. Identifying thermal issues early in the design cycle may allow the design team to consider available thermal mitigation options in the initial PCB design. The board-level design with FPGA components can be challenging with larger device packages supporting more than 900 designer-assignable I/O pins. There are many considerations an FPGA designer must make during the board layout process for large FPGA devices. The FPGA designer must know and understand important signal integrity issues that have become a critical part of FPGA design. Good signal-integrity practices will limit the amount of cross-talk, ground bounce, and ringing by controlling and implementing proper noise margins, impedance matching, and decoupling. Signal-integrity is especially critical for high-speed design. Power generation for FPGA components is becoming increasingly challenging as the level of integration and performance of devices continues to increase. A common design approach is to generate the required power levels very close to the FPGA.