Register-Transfer-Level Design for Application-Specific Integrated Circuits

Abstract

Over the years, a rapid growth has been witnessed in electronics semiconductor industry because of the huge demand for system-level designs. System-level designs are prominently used for various applications such as high-performance computing, controls, telecommunications, image and video processing, consumer electronics and others. Hence to accomplish such applications using very large-scale integration (VLSI) design, it is recommended to have an efficient register-transfer-level (RTL) design abstraction, as it can provide a low power and high-performance outcome (Wu and Liu in IEEE Trans Very Large Scale Integr (VLSI) Syst 6:707–718, Wu and Liu 1998). In digital integrated circuit (IC) design, RTL models a synchronous digital circuit in terms of the flow of digital signals or data between hardware registers and the logical operations performed on these signals. RTL abstraction is used in hardware description languages (HDLs) to create high-level representations of a circuit (Chinedu et al. in 3rd IEEE international conference on adaptive science and technology (ICAST 2011). IEEE, pp 262–267, Chinedu et al. 2011). From these lower-level representations, ultimately actual circuitry can be derived. Design at the RTL level is a typical practice in modern digital system designs. This chapter mainly focuses on design of RTLs for application-specific integrated circuits (ASICs) and how it differs for field-programmable gate arrays (FPGAs). The examples and modules discussed in this chapter are written in HDL, viz. Verilog language.