Faults Identification in Digital Counter Using Naïve-Bayes’ Algorithm

Abstract

This paper elaborates on the implementation of the Naïve Bayes Algorithm to identify the faults occurrence in the digital counter circuits. The digital counters are circuits utilized to count the values in increasing order, decreasing order, or both directions. The digital counters find applications in real time from simple wristwatches to the industrial conveyor belt that is automated based on timings. The fault happening in the digital counter circuit is to be identified using Fault detection methods such as modular redundancy methods and error detection methods. With the advent of Artificial Intelligence algorithms, the identification of faults and errors in circuits is attained rapid manner. Though there are several machine learning algorithms such as Decision trees, Random Forest, K-Nearest Neighbor, and Support Vector Machines, the naïve Bayes algorithm is an easy and efficient algorithm to identify the errors in the circuits. This work concentrates on the naïve Bayes algorithm by developing the HDL code to predict the faults in the counter circuits. The proposed HDL code is validated for parameters namely power, area, and timing using the EDA tools.