Counter Circuit Research Articles

Design of ternary counter based on adiabatic domino circuit

By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.

CMOS-based active RC sinusoidal oscillator with four-phase quadrature outputs and single-resistance-controlled (SRC) tuning laws

This paper proposes a very compact CMOS realization of active RC sinusoidal oscillator capable of generating four quadrature voltage outputs. The oscillator is based on the cascade of lossless and lossy integrators in loop. The governing laws for the condition of oscillation (CO) and the frequency of oscillation (FO) are single-resistance-controlled (SRC) and which allow independent FO tuning. Unlike previously reported SRC-based sinusoidal oscillators based on the active building block (ABB) based approach and which aim at reducing the number of employed ABBs, this direct CMOS realization provides a much reduced transistor count circuit and consequently offers a low power solution. A comparison with previously reported SRC oscillators in terms of number of transistors and current consumption has been provided. As a design example, a 160.2 kHz oscillator (typical process, T = 27 °C) with 82 μW power consumption is designed in 65 nm CMOS technology with supply voltage of ±0.5 V.

Ensuring a High Quality Digital Device through Design for Testability

An electronic device is reliable if it is available for use most of the times throughout its life. The reliability can be affected by mishandling and use under abnormal operating conditions. High quality product cannot be achieved without proper verification and testing during the product development cycle. If the design is difficult to test, then it is very likely that most of the faults will not be detected before it is shipped to the customer. This paper describes how product quality can be improved by making the hardware design testable. Various designs for testability techniqueswere discussed. A three bit counter circuit was used to illustrate the benefits of design for testability by using scan chain methodology.

Design of Bending Fatigue Machine for Flexible Electronics

According to the current requirements of bending fatigue test for flexible electronics, a bending fatigue machine based on SCM (single chip Microcomputer) has been designed. using stepper motor driving screw nut body as loading mechanism, improve the accuracy of the structure effectively by gaps eliminator, and achieve the requirement of precision control by using fraction driving technology in the motor control. Photoelectric counter and electrical signals detection circuit have also been designed to achieve unattended function. This design plays an important role in the following testing process.

A Study on Self Repairing for Fast Fault Recovery in Digital System by Mimicking Cell

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

Design of Ternary Clocked Adiabatic Synchronous Reversible Counter

Based on the study of synchronous counter and adiabatic circuits, a new design scheme of ternary adiabatic synchronous reversible counter is proposed. According to the theory of three essential circuit elements, circuit structure of four-bit ternary adiabatic synchronous reversible counter is realized by using NMOS transistors with different thresholds and cross-storage structure and combining with the principle of energy recovery. Computer simulation results indicate that the designed circuits have correct logic function. Compared with traditional CMOS counter, the average power consumption of circuits saves up to 67.5%.

Design and implementation of readout circuit on glass substrate with digital correction for touch‐panel applications

Abstract— A readout circuit on glass substrate with digital correction, which contains a transconductance amplifier, counter, and digital correction circuit, has been designed for touch‐panel applications for 3‐μm low‐temperature polysilicon (LTPS) technology. The voltage difference as a result of a change in capacitance due to a touch event is converted to current by a transconductance amplifier. By charging and discharging the capacitor in the counter, the counter displays different digital‐output codes according to touch or non‐touch events. Furthermore, not only can the touch or non‐touch event be distinguished, but also the influence of LTPS process variation can be compensated by a digital correction circuit in the proposed readout circuit.

The Non-Destructive Measurement Instrument for Material Thickness

In a variety of materials, the ultrasonic propagation velocity is different. Using ultrasonic reflection principle in the material, the measuring instrument detected the thickness of the measured object. AT89C51 microcontroller as the system core, with ultrasonic probe, transmitter circuit, receiver circuit, counter circuit, LCD display circuit together, completed the measurement of materials thickness. The measurement range was up to a 1.2 ~ 200mm. Practice shows that the instrument is low cost, high speed, high precision, reliability, adaptability, etc. So it has broad application prospects.

A current-mode multi-valued adder circuit for multi-operand addition

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

Si PIN X-ray photon counter

A Si PIN detector for visible light detection, instead of a Geiger-Muller tube, is applied to X-ray photon counting. We counted radiation from a checking source of a Geiger-Muller counter with a Si PIN counter and with a Geiger-Muller counter. White X-ray of energy up to 20 keV emitted from a pyroelectric X-ray emitter was also counted, and the Si PIN X-ray counter showed a similar curve of count rate versus source distance in both measurements. Pulse counting was performed by spectroscopy circuits. An audio digitizer with computer software for signal processing was also used to simplify the photon counter. A plot of count rate versus time was obtained with this setup. With simple pulse counting circuits, Si PIN X-ray counters have advantages such as compact structure, low cost and easy application. Copyright © 2011 John Wiley & Sons, Ltd.

Wind Power Grid Integration of an IPMSG using a Diode Rectifier and a Simple MPPT Control for Grid-Side Inverters

In this paper, a 1.5 kW Interior Permanent Magnet Synchronous Generator (IPMSG) with a power conditioner for the grid integration of a variable-speed wind turbine is developed. The power-conditioning system consists of a series-type 12-pulse diode rectifier powered by a phase shifting transformer and then cascaded to a PWM voltage source inverter. The PWM inverter is utilized to supply sinusoidal currents to the utility line by controlling the active and reactive current components in the q-d rotating reference frame. While the q-axis active current of the PWM inverter is regulated to follow an optimized active current reference so as to track the maximum power of the wind turbine. The d-axis reactive current can be adjusted to control the reactive power and voltage. In order to track the maximum power of the wind turbine, the optimal active current reference is determined by using a simple MPPT algorithm which requires only three sensors. Moreover, the phase angle of the utility voltage is detected using a simple electronic circuit consisting of both a zero-crossing voltage detecting circuit and a counter circuit employed with a crystal oscillator. At the generator terminals, a passive filter is designed not only to decrease the harmonic voltages and currents observed at the terminals of the IPMSG but also to improve the generator efficiency. The laboratory results indicate that the losses in the IPMSG can be effectively reduced by setting a passive filter at the generator terminals.

Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating

Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.

A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver

A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78% relative to pure Vernier delay line structure with a wide measurement range. The counter circuit occupies an area of 19 mum times 61 mum in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The power supply rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. The core circuit occupies an area of only 0.5 mm times 0.15 mm with the 90-nm CMOS process. The Gaussian and uniform distributions jitter is verified at a 5-ps timing resolution and a 2.5-GHz input clock frequency .

Design and Test of Express Elevator Control System

In order to meet the increasing requirements for express elevator control system and its intelligence and security, ARM chip is applied to construct hardware platform of elevator's main-board in this paper. BootLoader and the uCLinux are transplanted to this platform, and CAN-Bus and other related drivers are designed. A single elevator's operation algorithm is presented to achieve the elevator control logic. And the store and access of parameters of elevator are accomplished by real-time SQLite database. The main high-speed counting circuit is designed based on CPLD while the auxiliary one is based on AVR MCU, which guarantee the stability and reliability of the system. The operational results in elevator simulator verify the feasibility and efficiency of the control system.

The Combinational and Sequential Adiabatic Circuit Design and Its Applications

In this paper, a new design of adiabatic circuit, called the quasi-static efficient charge recovery logic (QSECRL) is proposed. To achieve minimum energy consumption, this paper proposes a technique to reduce channel resistance and remove diodes from the signal path. This design method can be implemented in both combination logic and sequential logic. The counter circuit and the 8-bit carry look-ahead (CLA) circuit, a more complex circuit, are selected to evaluate this proposed design. All simulations in this paper have been implemented by SPICE with the 0.8 μm MOSIS technology MOS transistor model under 2-volt (peak-peak) sinusoidal power-clock supply. The results show significantly improved performance of the 8-bit CLA circuit with 20---30 fJ and 70 fJ energy consumption at 10---100 MHz and 500 MHz operating frequency, respectively.

Multi-Fringe Counting Technique of Millimeter-Wave Interferometer System for KSTAR

A 280 GHz single-channel horizontal millimeter-wave interferometer system has been installed for plasma electron density measurements on the Korea Superconducting Tokamak Advanced Research (KSTAR). An electron density of plasma is measured on double-path horizontal line with triangular geometry. A cassette system contains two vacuum windows was installed on median port for these purpose. Maximum line-integrated electron density of first plasma is set to 1019 m-2 in this geometry. Since a line density of single-fringe in 280 GHz is 2 × 1018 m-2, a multi-fringe counting circuit has been adopted for a fringe-jump compensation. Measured IF signals are divided into 4 channels which has fringe counting capability of 1, 2, 4 and 8 fringes, respectively. A phase difference between IF signals is converted to DC voltage in each channel according to its fringe coverage. A fringe-jump analysis algorism has been developed for a discrimination of real fringe-jump from noise signal. An electron density of the KSTAR first plasma has been measured and analyzed using this system. Upon these results, an advanced fringe counting scheme will be proposed in this paper.

Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System

Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 μm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500 * 750 μm chip area for the 100―400 MHz measurement range.

Comment on “Voltage-Mode All-Pass Filters Including Minimum Component Count Circuits”

This comment is related to the recently published article “Active and Passive Electronic Components” by S. Maheshwari (2007), which presents single current differencing buffered amplifier (CDBA) and current-controlled current differencing buffered amplifier- (CC-CDBA-) based first-order voltage-mode (VM) all-pass filtering (APF) sections. The paper is reviewed, and additional first-order APF realizations have been proposed.

High-speed single flux-quantum up/down counter for neural computation using stochastic logic

We propose the high-speed single flux-quantum(SFQ) up/down counter for the neural computation using stochastic logic. Up and down signals are counted by two independent counters, respectively. The proposed counter circuit can count SFQ signals of 50GHz with large operation margins. To realize the up/down counter, we fabricated a 2-bit up counter circuit and a 2-bit down counter circuit as basic blocks by Nb integrated circuits. The low-speed test results of these circuits show correct operations. We also measured dc voltages of Josephson transmission lines to investigate the responses of carry operations for SFQ pulse trains. The results show that the counter circuits have potential to count 144GHz SFQ pulses.

Counting. Part 2

The authors continue their series of articles on making design decisions in electronics by looking at alternative approaches to implementing counting circuits that give accurate results despite having to cope with noisy input signals.