Design of Ternary and Quaternary Asynchronous Up/Down Counter using CNTFET

Abstract

This paper presents designs of ternary and quaternary up/down counters of single and multiple digits using CNTFET. The proposed counters have a special feature of counting in dual mode; up counting and down counting which makes these designs distinct from other existing designs. The proposed counters are designed using ternary/quaternary D flip-flops and a dynamic successor-predecessor circuit. The D flip-flops are built using standard ternary/quaternary inverters (STI/SQI) with an additional reset feature. The proposed dynamic successor-predecessor circuit has the capability of acting either as a successor or as a predecessor circuit based on a control signal. Counter circuits of multiple digits have been achieved with the help of a few additional transistors along with the single-digit counter circuits. All the proposed designs have been simulated in HSPICE using Stanford University’s 32 nm CNTFET model and simulation results have been noted. When compared with existing designs, the proposed designs show improvements in power and energy efficiency.