Design Compiler Research Articles

Perspective and Opportunities of Modulo 2n−1 Multipliers in Residue Number System: A Review

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.

Shared Pattern History Tables in Multicomponent Branch Predictors With a Dealiasing Cache

In this letter, we study the problem of designing multicomponent branch predictors for low-resource embedded systems. The highlight of our design is a shared pattern history table with a tiny dealiasing cache for intercomponent interference resolution. Experiments on the CBP-5 traces are shown to record the performance in terms of prediction accuracy. Synthesis results generated using the Synopsys design compiler with TSMC 90-nm libraries confirm the area and power benefits of our design.

High speed low area OBC DA based decimation filter for hearing aids application

This brief presents a decimation filter for hearing aid application using distributed arithmetic (DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA based finite impulse response (FIR) filter with a shared look-up table (LUT) updating scheme. The size of the LUTs in DA increases exponentially with the order of filters. Shared LUT based DA structure is a solution to reduce this large memory requirement for higher order filters. The proposed shared LUT updating scheme uses LUT partitioning in which coefficients are spilt into small length vectors and it ensures a drastic reduction in the size of LUTs. The proposed DA filter is synthesized on CMOS 90 nm technology using Synapsis ASIC Design Compiler. The proposed design achieves high speed at a reduced area-delay product (ADP) when compared with recent designs. The proposed architecture is implemented and tested on Virtex 5vsx95-1ff1136 FPGA and the results show that the proposed design involves less number of slices and offers high speed than existing designs. A three-stage decimation filter of hearing aids is designed with the proposed FIR filter and is implemented on the target device by Matlab simulink and Xilinx system generator.

A Secure Modular Division Algorithm Embedding with Error Detection and Low-Area ASIC Implementation

Modular division operation has important application in public-key cryptosystems. It is the most complex and time-consumed operation in RSA and ECC. Its secure and efficient implementation greatly affects the secure and performance of these cryptosystems. In this paper, a modular division algorithm embedding with error detection is proposed. Four computing types of ASIC implementation architectures (Type-8, Type-16, Type-32, Type-64) are explored to seek the optimal tradeoff among error detection ratio, time overhead and hardware overhead. These implementation architectures are modeled in Verilog language and synthesized using Synopsys Design Compiler with OSU 90 nm CMOS standard cell library. Experiment results show that the proposed Type-64 can get almost 100% error detection probability with an average of 24.71% extra area overhead and 0.52% time overhead. In addition, for the implementation of single modular division module, the proposed Type-64 architecture saves 60.74% area overhead on average with a slight decrease of throughput rate compared with the state-of-the-art re- search. This implementation not only greatly reduces the area overhead of modular division but also improves the security of modular division implementation.

Superscalar Pipelined Matrix Multiplier in VHDL

Parallel processing is used by simultaneous information processing to boost the computing velocity of the computer system. Parallel processing is implemented by pipeline processing.. In this paper we presented design of a A[100][100] x B[100][100] Pipelined Matrix Multiplier and its results is stored in P[100][100] matrix. We present design and stimulate a functional Pipelined Matrix Multiplier Unit. By which we can learn about the working of Pipelined Matrix Multiplier and how pipelining works. We also get the knowledge of clock timing and learn to make a timing critical design. In this Pipelined Matrix Multiplier Unit design we use design compiler, which is a module of Synopsys tools that uses lsi_10k library and BCCOM method to synthesis the design and simulate the design through VCS compiler.

VLSI Architecture for Enhanced Approximate Message Passing Algorithm

Compressed sensing (CS) enables the reconstruction of sparse signals from a small number of linear measurements. However, sparse signal recovery algorithms require significant computational effort, even for problems of moderate size, and make their hardware realization a highly challenging task. In this paper, we present a novel architecture for the reconstruction of the sparse signal using the recently proposed Enhanced Approximate Message Passing (EAMP) algorithm. The EAMP algorithm shows better performance in terms of convergence rate and sparsity measurement trade-off as compared to AMP, IST and IHT techniques. The execution time of the proposed design has been reduced by maximizing parallelism with an appropriate level of unfolding. It receives CS measurements (y) and the number of non-zero elements (K) in the input vector from the encoder. Depending on the value of K, one sensing matrix (Φ j ) is selected from the code book Φ. The reconstruction algorithm (EAMP) recovers the input vector (s) by using y and Φ. Bitonic sorting has been used to identify the thresholding value in the EAMP algorithm. The proposed architecture for EAMP algorithm has been synthesized using Synopsys design compiler with 65 nm technology CMOS standard cell libraries. It occupies 719.15 KGE and consumes 315.5 mW power at a frequency of 400 MHz. It is suitable for any arbitrary sparsity-based signal restoration and CS problems.

High-Throughput Low-Area Hardware Design of Authenticated Encryption with Associated Data Cryptosystem that Uses ChaCha20 and Poly1305

In this paper, the hardware design of a low area and a high throughput ChaCha20-Poly1305 that performs the dual authentication-encryption function for a secured communication within hardware devices is presented. Cryptographic algorithms- ChaCha20 stream cipher and Poly1305, enhance security margins and achieve higher performance measures on a wide range of software platforms and has proven superior to its counterpart, the AES, in the software domain. This relatively new stream cipher is compared to the benchmark AES, has recently been standardized but their implementations in hardware have had very little to not very desirable results particularly in terms of area. For this reason, it is therefore an active field to make such algorithms hardware friendly. This research presents a compact, low-area and high throughput chacha20-Poly1305 Authenticated Encryption with Associated Data (AEAD) design. The core architecture consists of the ChaCha20-Poly1305 algorithm. The simplified quarter round designed in the proposed architecture uses the addition, rotation and exclusive-or algorithms operators (gates). This proposed architecture provides an improvement in the operating frequency and area. The architecture was modeled and simulated with Verilog HDL and Modelsim tools for functional and timing correctness. The hardware architecture designed was synthesized with Xilinx‟s Synthesis Tool (XST) and Synopsis‟ Design Compiler (DC) using the 0.18µm CMOS standard Cell library. The resulting hardware area in terms of gate equivalent is approximately 11KGE for chacha20 and 21KGE for Poly1305. The design operates at maximum frequency of 420 MHz and 870 MHz for the ChaCha20 and Poly1305 respectively. The proposed design presented in this paper additionally functions at a throughput of approximately 8 Gbps for ChaCha20 with an overall efficiency of 2.35 Kbps/GE when ChaCha20 and Poly1305 are combined into the AEAD_ChaCha20_Poly1305 authenticated encryption core.

Low Power High Throughput Memory Less Adaptive Filter using Distributed Arithmetic

This paper briefs an area efficient, low power and high throughput LMS adaptive filter using Distributed Arithmetic architecture. The throughput is increased because of parallel updating of filter coefficient and computing the inner product simultaneously. Here we have proposed memory-less design of distributed arithmetic (MLDA) unit. The proposed design uses 2:1 multiplexer’s architecture to replace LUT of the conventional DA to reduce the overall area of the filter. Enhanced compressor adder is used for accumulation of the partial products, which further helps to reduce the area. Parallel updating of the generation and accumulation enhance the throughput of the design. The proposed architecture requires more than half area that required for the existing LUT based inner product block. The proposed design is implemented in synopsis design compiler and the result shows that the area decreased by 52.7% and also the MUX based DA for the Adaptive filter causes 69.25% less power consumption for filter tap N=16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP).

Multiplication Technique in Residue Number System

This paper presents the modulo multiplication technique in residue number system (RNS) using Vedic mathematics. Residue number system supports fast mathematsical computation. In this paper, the use of the combination of RNS and Vedic mathematics has improved the computation time for modulo multiplication operation. The proposed modulo multiplier is implemented in VHDL and synthesized using Xilinx ISE 14.1.The performance comparison analysis in terms of area, power and delay is done between the proposed technique and direct computation. The performance of the multiplier circuit has been compared using the 32 nm standard cells available in Synopsys Design Compiler. The presented Vedic modulo multiplier is efficient in terms of speed for large input data sizes

An α-factor architecture for RS decoder implemented on 90 nm CMOS technology for computer computing applications devices

In Computing devices in the world wide, where number of computing and communication systems are increased rapidly. In the channel noise has greater impact on the messages or data transmitted through the wired/wireless network. The Reed–Solomon (RS) decoder plays a vital role in removing the error from the received messages or data. The RS decoder has four main blocks, namely, Syndrome Computation (SC) block, Key Equation Solver (KES) block, Chien Search (CS) block and Forney Algorithm (FA) block. The researchers have thrown a number of works on each and every block of RS decoder. Moreover, the parallel and pipelined RS decoder shows a greater improvement in terms of gate element, latency, coding gain and throughput. Although this architecture has higher performance gain, the computation complexity in the SC block is not addressed. This paper presents an efficient architecture to compute the α-factor of SC blocks in RS decoder. The proposed RS decoder is developed using Verilog HDL (Hardware Description Language) and synthesized in Synopsys Design Compiler (DC). The proposed architecture is implemented in 90 nm CMOS technology and the results are evaluated in terms of gate count, clock rate, latency and throughput. The evaluated results of the proposed decoder show a remarkable improvement when compared with a conventional RS decoder.

HDL Implementation of Five Moduli Residue Number System

The demand for residue number system (RNS) is increasing day by day because of its high speed and fault tolerant characteristics. RNS encodes a large number into group of small numbers, which consequently increases the overall data processing rate. This paper presents an analysis of the forward converter designed using ripple carry adder (RCA), carry save adder (CSA), and half adder-like (HAL), for the figure of merits area, delay, and power for five moduli set: 2n-1, 2n, 2n+1, 2n+1-1, and 2n-1-1 with the standard cells at 90 nm technology. The designing of different blocks has been done in Verilog-HDL. The area, delay, and power of the implemented circuits are obtained using the Synopsys Design Compiler at 90 nm technology node, while VCS is used for verification. It is observed that the area of the architecture using CSA is less, whereas power utilization and timing behavior are better in HAL.

A User Feedback Centric Approach for Detecting and Mitigating God Class Code Smell Using Frequent Usage Patterns

Code smells are the fragments in the source code that indicates deeper problems in the underlying software design. These code smells can hinder software evolution and maintenance. Out of different code smell types, the God Class (GC) code smell is one of the many important code smells that directly affects the software evolution and maintenance. The GC is commonly defined as a much larger class in systems that either know too much or do too much as compared to other classes in the system. God Classes are generally accidentally created overtime during software evolution because of the incremental addition of functionalities to it. Generally, a GC indicates a bad design choice and it must be detected and mitigated in order to enhance the quality of the underlying software. However, sometimes the presence of a GC is also considered a good design choice, especially in compiler design, interpreter design and parser implementation. This makes the developer’s feedback important for the correct classification of a class as a GC or a normal class. Therefore, this paper proposes a new approach that detects and proposes refactoring opportunities for GC code smell. The proposed approach makes use of different code metrics in combination along with utilizing user feedback as an important aspect while correctly identifying the GC code smell. The proposed approach that considers combined use of code metrics, is based on two newly proposed code metrics in this paper. The first newly proposed metric is a new approach of measuring the connectivity of a given class with other classes in the system (also termed as coupling). The second newly proposed code metric is proposed to measure the extent to which a given classes make use of foreign member variables. Finally, the proposed approach is also empirically evaluated on two standard open-source commonly used software systems. The obtained result indicates that the proposed approach is capable of correctly identifying the GC code smell.

Simplifying Transactional Memory Support in C++

C++ has supported a provisional version of Transactional Memory (TM) since 2015, via a technical specification. However, TM has not seen widespread adoption, and compiler vendors have been slow to implement the technical specification. We conjecture that the proposed TM support is too difficult for programmers to use, too complex for compiler designers to implement and verify, and not industry-proven enough to justify final standardization in its current form. To address these problems, we present a different design for supporting TM in C++. By forbidding explicit self-abort, and by introducing an executor-based mechanism for running transactions, our approach makes it easier for developers to get code up and running with TM. Our proposal should also be appealing to compiler developers, as it allows a spectrum of levels of support for TM, with varying performance, and varying reliance on hardware TM support in order to provide scalability. <?tight?>While our design does not enable some of the optimizations admitted by the current technical specification, we show that it enables the implementation of robust support for TM in a small, orthogonal compiler extension. Our implementation is able to handle a wide range of transactional programs, delivering low instrumentation overhead and scalability and performance on par with the current state of the art. Based on this experience, we believe our approach to be a viable means of reinvigorating the standardization of TM in C++.

Tailored heuristics in adaptive large neighborhood search applied to the cutwidth minimization problem

The cutwidth minimization problem (CMP) consists in determining a linear layout (i.e., a one-dimensional arrangement), of the vertices of a graph that minimizes the maximum number of edges crossing any consecutive pair of vertices. This problem has applications, for instance, in design of very large-scale integration circuits, graph drawing, and compiler design. The CMP is an NP-Hard problem and presents a challenge to exact methods and heuristics. In this study, the metaheuristic adaptive large neighborhood search is applied to the CMP. The computational experiments include 11,786 benchmark instances from four sets in the literature, and the obtained results are compared with state-of-the-art methods. The proposed method was demonstrated to be competitive, as it matched most optimal and best known results, improved some of the (not proved optimal) best known solutions, and provided the first upper bounds for unsolved instances.

Towards a simple and safe Objective Caml compiling framework for the synchronous language SIGNAL

This paper presents a simple and safe compiler, called MinSIGNAL, from a subset of the synchronous dataflow language SIGNAL to C, as well as its existing enhancements. The compiler follows a modular architecture, and can be seen as a sequence of source-to-source transformations applied to an intermediate representation which is named Synchronous Clocked Guarded Actions (S-CGA) and translation to sequential imperative code. Objective Caml (OCaml) is used for the implementation of MinSIGNAL. As a modern functional language, OCaml is adapted to symbolic computation and so, particularly suitable for compiler design and implementation of formal analysis tools. In particular, the safety of its type checking allows to skip some verification that would be mandatory with other languages. Additionally, this work is a basis for the formal verification of the compilation of SIGNAL with a theorem prover such as Coq.

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

The advent of data proliferation and electronic devices gets low execution time and energy consumption software in the spotlight. The key to optimizing software is the correct choice, order as well as parameters of optimization transformations that has remained an open problem in compilation research for decades for various reasons. First, most of the transformations are interdependent and thus addressing them separately is not effective. Second, it is very hard to couple the transformation parameters to the processor architecture (e.g., cache size) and algorithm characteristics (e.g., data reuse); therefore, compiler designers and researchers either do not take them into account at all or do it partly. Third, the exploration space, i.e., the set of all optimization configurations that have to be explored, is huge and thus searching is impractical. In this paper, the above problems are addressed for data-dominant affine loop kernels, delivering significant contributions. A novel methodology is presented reducing the exploration space of six code optimizations by many orders of magnitude. The objective can be execution time (ET), energy consumption (E) or the number of L1, L2 and main memory accesses. The exploration space is reduced in two phases: firstly, by applying a novel register blocking algorithm and a novel loop tiling algorithm and secondly, by computing the maximum and minimum ET/E values for each optimization set. The proposed methodology has been evaluated for both embedded and general-purpose CPUs and for seven well-known algorithms, achieving high memory access, speedup and energy consumption gain values (from 1.17 up to 40) over gcc compiler, hand-written optimized code and Polly. The exploration space from which the near-optimum parameters are selected is reduced from 17 up to 30 orders of magnitude.

An Efficient Hardware Accelerator for the MUSIC Algorithm

As a classical DOA (direction of arrival) estimation algorithm, the multiple signal classification (MUSIC) algorithm can estimate the direction of signal incidence. A major bottleneck in the application of this algorithm is the large computation amount, so accelerating the algorithm to meet the requirements of high real-time and high precision is the focus. In this paper, we design an efficient and reconfigurable accelerator to implement the MUSIC algorithm. Initially, we propose a hardware-friendly MUSIC algorithm without the eigenstructure decomposition of the covariance matrix, which is time consuming and accounts for about 60% of the whole computation. Furthermore, to reduce the computation of the covariance matrix, this paper utilizes the conjugate symmetry property of it and the way of iterative storage, which can also lessen memory access time. Finally, we adopt the stepwise search method to realize the spectral peak search, which can meet the requirements of 1° and 0.1° precision. The accelerator can operate at a maximum frequency of 1 GHz with a 4,765,475.4 μm2 area, and the power dissipation is 238.27 mW after the gate-level synthesis under the TSMC 40-nm CMOS technology with the Synopsys Design Compiler. Our implementation can accelerate the algorithm to meet the high real-time and high precision requirements in applications. Assuming that the case is an eight-element uniform linear array, a single signal source, and 128 snapshots, the computation times of the algorithm in our architecture are 2.8 μs and 22.7 μs for covariance matrix estimation and spectral peak search, respectively.

Encrypted Tag Design for RFID Systems

The wireless implantable RFID tag combines wireless communication technology, medical sensor technology, and data conversion technology to achieve continuous detection of body indicators. The implantable tag system includes a small signal detection circuit, a readout circuit to complete sensor data acquisition and conversion, and a digital baseband and RF front end to perform communication with an external reader. The digital baseband processor handles communication protocols, controls communication flow, configures the RF front end, and controls the sampling of human body data by the ADC, which is a key component of the implantable tag system.Based on the 13.56MHz IS015693 radio frequency identification protocol, this paper designs and implements an encrypted tag baseband. Through the analysis of the protocol and the application requirements of the tag, the system architecture of the digital baseband is formulated. Subsequently, the functional logic was verified using Cadence’s Incisive EDA tool and synthesized using Synopsys’ EDA synthesis tool Design Compiler. The simulation results show that the logic function is correct. The synthesis tool report shows that under the 0.13um process, timing closures. The setup time and hold time meet the requirements.

A Low-Cost Design of 2D Median Filter

The median filter plays an important role in image processing for noise removing. To enhance the operating speed, hardware implementation of median filter on field programmable gate arrays (FPGA) or application specific IC (ASIC) are necessary and inevitable. This paper presents a low-cost and high-throughput hardware design for two-dimensional (2D) median filter. Two techniques are employed to reduce circuit area. One is the parallel three-valued sorting method for reducing the number of pipelined registers under constant speed, and the other is the functional sharing method used to implement median value sorting with the least number of comparisons. The proposed 2D median filter is implemented by two different synthesized methods. One is synthesized by Synopsys Design Compiler with the TSMC 90nm cell library (ASIC design) and the other is synthesized by Xilinx FPGA Virtex7 XC7VX690T (FPGA design). Experimental results show that the area cost of the proposed design is reduced more than 30% on average in comparison to the previous designs.

A new approach for 1-D and 2-D DWT architectures using LUT based lifting and flipping cell

In this paper, area and power efficient lifting and flipping discrete wavelet transform (DWT) architectures are proposed. DWT architectural metrics such as critical path delay, area of utilization, power consumption are mainly dependent on the arithmetic components such as adders and multipliers. They constitute the data-path of the DWT structure. A multiplier of the DWT data-path plays major role in basic lifting, flipping cells and further it demands optimization. In this work, an area and power efficient lifting and flipping cells are implemented using look up table (LUT) based multipliers. The proposed DWT architectures are implemented in gate level Verilog HDL and are synthesized using Cadence RC design compiler. Based on the area, delay, and power results obtained from post synthesis, parameters like area delay product (ADP) and power delay product (PDP) are computed. The ADP and PDP values prove that the proposed LUT based architectures are efficient over recently projected lifting and flipping DWT architectures.