An α-factor architecture for RS decoder implemented on 90 nm CMOS technology for computer computing applications devices

Abstract

In Computing devices in the world wide, where number of computing and communication systems are increased rapidly. In the channel noise has greater impact on the messages or data transmitted through the wired/wireless network. The Reed–Solomon (RS) decoder plays a vital role in removing the error from the received messages or data. The RS decoder has four main blocks, namely, Syndrome Computation (SC) block, Key Equation Solver (KES) block, Chien Search (CS) block and Forney Algorithm (FA) block. The researchers have thrown a number of works on each and every block of RS decoder. Moreover, the parallel and pipelined RS decoder shows a greater improvement in terms of gate element, latency, coding gain and throughput. Although this architecture has higher performance gain, the computation complexity in the SC block is not addressed. This paper presents an efficient architecture to compute the α-factor of SC blocks in RS decoder. The proposed RS decoder is developed using Verilog HDL (Hardware Description Language) and synthesized in Synopsys Design Compiler (DC). The proposed architecture is implemented in 90 nm CMOS technology and the results are evaluated in terms of gate count, clock rate, latency and throughput. The evaluated results of the proposed decoder show a remarkable improvement when compared with a conventional RS decoder.