An Ultra High-Speed Reed-Solomon Decoder

Abstract

This paper presents an ultra high-speed Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block. The RS decoder features a high-speed, low-complexity PrME algorithm block for the key equation solver. The pipelined recursive structure enables us to implement the high-speed, low-complexity PrME algorithm block, which has only one processing element. Pipelining and parallelizing allow inputs to be received at very high data processing rates and outputs to be delivered at correspondingly high rates with minimum delay. This paper presents the key ideas applied to the design of ultra high-speed RS decoder architecture, especially that for achieving high throughput 80-Gb/s and reducing area complexity. The ultra high-speed 80-Gbit/s 16-channel RS decoder has been designed and implemented with the 0.13-/spl mu/m CMOS technology in a supply voltage of 1.2 V. The proposed RS decoder has a core gate count of 393 K and operates at a clock rate of 625 MHz.