Multiplication Technique in Residue Number System

Abstract

This paper presents the modulo multiplication technique in residue number system (RNS) using Vedic mathematics. Residue number system supports fast mathematsical computation. In this paper, the use of the combination of RNS and Vedic mathematics has improved the computation time for modulo multiplication operation. The proposed modulo multiplier is implemented in VHDL and synthesized using Xilinx ISE 14.1.The performance comparison analysis in terms of area, power and delay is done between the proposed technique and direct computation. The performance of the multiplier circuit has been compared using the 32 nm standard cells available in Synopsys Design Compiler. The presented Vedic modulo multiplier is efficient in terms of speed for large input data sizes