Optimized Parity-Based Error Detection and Correction Methods for Residue Number System

Abstract

Residue Number System (RNS) has been extensively used in high-speed applications. It inherits the advantages of parallelism and modularity, which lead to fault tolerance property. Since carry propagation is limited to each module in RNS, errors do not propagate inter-moduli. Indeed, due to the restriction in carry propagation and fault tolerance property, RNS can be promisingly fast and reliable that makes it a favorable encoding for the digital systems which are highly prone to noise like communication channels. By adding some extra moduli, the so-called redundant RNS (RRNS) is gained. Although several methods around RRNS have already been proposed in the literature, the structures without need for extra moduli have not been introduced yet. This paper addresses three Error Detection and Correction (EDC) schemes for RNS based on parity structures. Using these techniques, the low power fault-tolerant RNS methods with low complexity are presented. Synthesis results using 180[Formula: see text]nm CMOS standard cell library show that the proposed architectures for the three-moduli set [Formula: see text] are in average 17%, 52% and 44% more efficient than the conventional RRNS in terms of delay, power consumption, and area overhead, respectively, without losing the EDC capability.