A Secure Modular Division Algorithm Embedding with Error Detection and Low-Area ASIC Implementation

Abstract

Modular division operation has important application in public-key cryptosystems. It is the most complex and time-consumed operation in RSA and ECC. Its secure and efficient implementation greatly affects the secure and performance of these cryptosystems. In this paper, a modular division algorithm embedding with error detection is proposed. Four computing types of ASIC implementation architectures (Type-8, Type-16, Type-32, Type-64) are explored to seek the optimal tradeoff among error detection ratio, time overhead and hardware overhead. These implementation architectures are modeled in Verilog language and synthesized using Synopsys Design Compiler with OSU 90 nm CMOS standard cell library. Experiment results show that the proposed Type-64 can get almost 100% error detection probability with an average of 24.71% extra area overhead and 0.52% time overhead. In addition, for the implementation of single modular division module, the proposed Type-64 architecture saves 60.74% area overhead on average with a slight decrease of throughput rate compared with the state-of-the-art re- search. This implementation not only greatly reduces the area overhead of modular division but also improves the security of modular division implementation.