HDL Implementation of Five Moduli Residue Number System

Abstract

The demand for residue number system (RNS) is increasing day by day because of its high speed and fault tolerant characteristics. RNS encodes a large number into group of small numbers, which consequently increases the overall data processing rate. This paper presents an analysis of the forward converter designed using ripple carry adder (RCA), carry save adder (CSA), and half adder-like (HAL), for the figure of merits area, delay, and power for five moduli set: 2n-1, 2n, 2n+1, 2n+1-1, and 2n-1-1 with the standard cells at 90 nm technology. The designing of different blocks has been done in Verilog-HDL. The area, delay, and power of the implemented circuits are obtained using the Synopsys Design Compiler at 90 nm technology node, while VCS is used for verification. It is observed that the area of the architecture using CSA is less, whereas power utilization and timing behavior are better in HAL.