Abstract
In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL styles. Moreover in this paper, 32 bit adders such as Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Carry Save Adder (CSA), Carry Skip Adder (CSKA) and Brent Kung Adder (BKA) are realised using proposed ECRL and 2PASCL adiabatic full adders. All the adders are implemented and simulated using TANNER EDA tool 22nm technology, parameters like power, area, delay and power delay product (PDP) of all the adders are observed at different operating frequencies, with supply voltage of 0.95 v and load capacitance of 0.5 pF. The observed parameters are compared with the existing adiabatic full adder designs and concluded that the proposed adiabatic full adders have the advantages of less power, delay and transistor count. In conclusion ECRL full adder is 31% faster, has equal PDP and less area than 2PASCL full adder. At 1000MHz ECRL 32 bit carry save adder is having less delay among all the 32 bit adder and 65% less PDP than 2PASCL adder and it is concluded that ECRL 32 bit carry save adder can be selected for implementation of circuits that can be used in portable mobile applications.
Highlights
The usage of battery-operated portable devices has been increased drastically
All the adders i.e 1 bit Efficient Charge Recovery Logic (ECRL),2PASCL full adder and 5 different 32 bit adders are implemented and simulated TANNER EDA tool at 22 nm technology with supply voltage Vdd = 0.95 volts and load capacitance = 0.5pF.Number of transistors for implementing full adders for selected adiabatic full adders are listed in table 1.The parameters like area, power consumed, delay and power delay product(PDP) are observed for proposed full adders at different operating frequencies and the comparison of parameters between existing and proposed adiabatic full adders are listed in the table 2.Fig .13.is the graph of PDP of different full adder designs for 2PASCL logic at different frequencies
At 1000MHz ECRL 32-bit carry save adder is having less delay among all the 32-bit adder and 65% less PDP than 2PASCL adder.so it is concluded that ECRL 32-bit carry save adder can be selected for implementation of multipliers, which plays a key role in signal processing at high frequency mobile applications
Summary
The usage of battery-operated portable devices has been increased drastically. The main reasons residing behind is that, the rapid scaling of device dimensions, demands growth of the operating frequency and processing capacity per chip which results in increased power dissipation [1][2]. In the literature many full adder designs are proposed and designed, the most basic design is the standard conventional static CMOS full adder high provides full voltage swing output with good driving capability It has drawback of high input capacitance, declined speed and more on chip area [6]. Another approach is pass transistor 16 T full adder cell design to reduce power consumption but this logic suffers from low output swing and cannot sustain low voltage operations [7].
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