Abstract
Adders are considered as the critical block in multipliers and other digital circuits. By improving the performance of the adder block, the overall system performance can be improved. Through this paper a correlative analysis of several adders like Carry Save Adder (CSaA), Carry Select Adder (CSeA), Carry Skip Adder (CSA), Ripple Carry Adder (RCA), Carry Look ahead Adder (CLA) designed and analyzed using Verilog HDL code. The performance metrics consider for comparison are area and delay. From the analysis performed, Carry Skip Adder has been concluded to be the better-performing one. The efficient full adder structure at the transistor level is identified namely 6T, 10T, 26T, and 24T. The identified transistor-level full adders are implemented in different block structures of 16 bit Carry skip adders to meet the better performing one. Simulation results show 8block CSA using 6T full adder is 37% efficient in the matter of delay and 8block CSA using 10T full adder is 35% efficient in the matter of power.
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