A novel implementation of high speed modified brent kung carry select adder

Abstract

VLSI technology is an emerging field in the current technological scenario due to its advancements in fields of systems architecture, analog and digital logic and adders are the basic building blocks in digital integrated circuit based designs. The existing Ripple Carry Adder (RCA) has the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead Adder (CLA) but they lead to increase in area. Carry Select Adder (CSLA) is a compromise between RCA and CLA in terms of area and delay. In this paper the logic operations involved in RCA based CSLA and Binary to Excess-1 Converter (BEC) based CSLA is analyzed to study the data dependence and to identify the redundant logic operations. The proposed design includes CSLA using parallel prefix adder. Parallel prefix adders are a tree structure based and are preferred to speed up the binary additions. Brent Kung (BK) adder is a parallel prefix adder which gives improved performance in terms of speed. A linear BK CSLA is designed and a modification is made in linear BK CSLA, by using BEC and BK with reduced delay. The designs are synthesized using Altera Quartus II Software.