VLSI Architecture for Enhanced Approximate Message Passing Algorithm

Abstract

Compressed sensing (CS) enables the reconstruction of sparse signals from a small number of linear measurements. However, sparse signal recovery algorithms require significant computational effort, even for problems of moderate size, and make their hardware realization a highly challenging task. In this paper, we present a novel architecture for the reconstruction of the sparse signal using the recently proposed Enhanced Approximate Message Passing (EAMP) algorithm. The EAMP algorithm shows better performance in terms of convergence rate and sparsity measurement trade-off as compared to AMP, IST and IHT techniques. The execution time of the proposed design has been reduced by maximizing parallelism with an appropriate level of unfolding. It receives CS measurements (y) and the number of non-zero elements (K) in the input vector from the encoder. Depending on the value of K, one sensing matrix (Φ j ) is selected from the code book Φ. The reconstruction algorithm (EAMP) recovers the input vector (s) by using y and Φ. Bitonic sorting has been used to identify the thresholding value in the EAMP algorithm. The proposed architecture for EAMP algorithm has been synthesized using Synopsys design compiler with 65 nm technology CMOS standard cell libraries. It occupies 719.15 KGE and consumes 315.5 mW power at a frequency of 400 MHz. It is suitable for any arbitrary sparsity-based signal restoration and CS problems.