Channel Length Direction Research Articles

Quantitative Analysis of Channel Width Effects on Electrical Performance Degradation of Top-gate Self-aligned Coplanar IGZO Thin-film Transistors under Self-heating Stresses

In this study, a quantitative analysis was conducted on the effects of channel width on electrical performance degradation induced by self-heating stress (SHS) in top-gate self-aligned coplanar indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). From the transfer and capacitance-voltage curves obtained before and after SHS, we revealed that the electrical performance of the TFT was nonuniformly degraded along the channel length direction and the degree of this degradation was more significant in TFTs with a wider channel width. The threshold voltage shift (ΔVSUBTH/SUB) under SHS in the fabricated IGZO TFT was mainly attributed to the increase in the density of shallow donor states and acceptor-like deep states in the IGZO active region and electron trapping into the fast and slow traps in the SiOSUBX/SUB gate dielectric. In addition, we conducted a decomposition of the SHS-induced ΔVSUBTH/SUB originated from each degradation mechanism using the subgap density of states-based ΔVSUBTH/SUB decomposition technique for TFTs with different channel widths. Although every ΔVSUBTH/SUB from each degradation mechanism increased as the channel width increased, increased electron trapping into the slow trap in the SiOSUBX/SUB gate dielectric was the dominant reason for the larger ΔVSUBTH/SUB under SHS in IGZO TFTs with a wider channel width.

Numerical investigation of field-effect control on hybrid electrokinetics for continuous and position-tunable nanoparticle concentration in microfluidics.

We introduce herein an effective way for continuous delivery and position-switchable trapping of nanoparticles via field-effect control on hybrid electrokinetics (HEK). Flow field-effect transistor exploiting HEK delicately combines horizontal linear electroosmosis and transversal nonlinear electroosmosis of a shiftable flow stagnation line (FSL) on gate terminals under DC-biased AC forcing. The microfluidic nanoparticle concentrator proposed herein makes use of a simple device geometry, in which an individual or a series of planar metal strips serving as gate electrode (GE) are subjected to a hybrid gate voltage signal and arranged in parallel between a pair of 3D driving electrodes. On the application of a DC-biased AC electric field across channel length direction, all the GE are electrochemically polarized, and the action of imposed hybrid electric field on the multiple-frequency bipolar counterions within the composite-induced double layer generates two counter-rotating induced-charge electroosmotic (ICEO) micro-vortices on top of each GE. Symmetry breaking in ICEO flow profile occurs once the gate voltage deviates from natural floating potential of corresponding GE. The gate voltage offset not only results in an additional pump motion of working fluid for enhanced electroosmotic transport but also directly changes the location of FSL where nanoparticles are preferentially collected by field-effect HEK. Our results of field-effect control on HEK are supposed to guide an elaborate design of flexible electrokinetic frameworks embedding coplanar metal strips for a high degree of freedom analyte manipulation in modern micro-total-analytical systems.

Modeling of thin-film transistor device characteristics based on fundamental charge transport physics

A model is described that enables the calculation of thin-film transistor (TFT) characteristics starting from fundamental considerations of charge transport. Starting from scattering mechanisms and trap distribution in a semiconductor, electric field and charge density distributions are calculated along the channel length direction. Output and transfer characteristics of a TFT can be calculated at any temperature. The model is quasi-two-dimensional and is based on multiple trap and release transport in the semiconductor active layer. Importantly, the charge transport models that constitute the basis of this paper are very sophisticated and operate at a level of depth and detail that go beyond most other studies on thin-film transistors. Contact resistance effects, often very important in TFTs, are included in the model. Simulation results are presented for several representative TFT dimensions and parameter sets. The model is designed for convenient use by the research community, and the source code as well as instructions are publicly available. The modular nature of the models allows for ease in changing the semiconductor parameters, transport mechanisms, contact barriers, etc.

Effect of fluid distribution along the channel length on the cooling performance of microchannel heat sink

Purpose The purpose of this study is to conduct research on a new kind of division microchannel heat sink (D-MCHS), which can distribute cooling water along the channel-length direction. First, the pressure drops in the D-MCHS with different division region numbers were compared. Then, the cooling performance of the D-MCHS with different division region numbers was also comparatively investigated. Finally, the temperature distribution on the bottom surface of the D-MCHS was analyzed. Design/methodology/approach First, experiments were conducted to investigate the numerical calculation method. Then, a three-dimensional steady, single-phase, laminar flow and solid-fluid conjugate heat transfer numerical model was used to research the flow and heat transfer characteristics in microchannels. Findings The pressure drop in the D-MCHS could be reduced by increasing the number of divided flow regions along the channel-length direction. The bottom average temperature of the D-MCHS could be simultaneously affected by the number of divided flow regions and the water flow rate. The thermal uniformity performance of the D-MCHS could be improved by increasing the number of division flow regions. The number of low-temperature and high-temperature areas on the bottom surface of the D-MCHS is corresponding to the division flow region number. Originality/value The D-MCHS exhibited a positive effect on the pressure drop decrease and thermal uniformity improvement. It not only keeps the electronic module working in a secure temperature environment but also consumes less pump power for a lower pressure drop.

Lateral profiling of gate dielectric damage by off-state stress and positive-bias temperature instability

Gate dielectric degradation caused by off-state stress (OSS) and positive-bias temperature instability (PBTI) was analyzed in terms of charge trapping inside the gate dielectric and at the interface. Under the same degree of stress voltage, the OSS damage caused more degradation of threshold voltage (VT) than the PBTI damage. When the two stresses were alternately applied to an n-channel MOSFET, they effectively produced a leftward shift in the VT. This was because a greater negative VT shift was produced by the OSS and a less positive VT shift was produced by the PBTI. By analyzing the characteristics of the gate induced drain leakage (GIDL), it was determined that charge trapping inside the gate dielectric was more localized on the drain side than on the source side after OSS, but was distributed at a relatively similar level along the channel length direction after PBTI. To analyze the interface traps caused by OSS and PBTI, charge pumping (CP) measurements were conducted to map their lateral distribution along the channel direction. The PBTI-induced interface traps were found to be symmetrically distributed on the source side and drain side, while the OSS-induced interface traps were more concentrated toward the drain side.

Degradation and Failure of Flexible Low-Temperature Poly-Si TFTs Under Dynamic Stretch Stress

Degradation and failure behaviors of the flexible low-temperature poly-Si (LTPS) thin film transistors (TFTs) under repetitive stretch stress parallel to channel length (L) direction are investigated. A geometric effect is observed in degradation of the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ), which depends on the channel width (W) and active area ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WL</i> ), while has a weak correlation with L. Three failure modes of TFTs are identified from their I-V characteristics: damage in the gate insulator (GI), channel traps generation, and metal line cracks. Failure statistics show that the GI failure has a low failure rate and follows the exponential distribution, while the other two modes have high failure rates in the early stage of the stretch cycles, and their failure distributions follow the limited failure population (LFP) model.

UTBB Thermal Coupling Analysis in Technological Node Level

The main goal of this work is to perform a first-time analysis of the thermal cross-coupling in a system composed by some devices in an integration node degree composed by advanced UTBB SOI MOSFETs through numerical simulations, validated with experimental data from the literature. In this analysis, it could be observed that devices located on the channel length direction provoke a reduced thermal coupling and devices with their drain region next to each other suffer of an increased thermal coupling due to the lumped thermal energy. It also could be observed a degradation in some electrical parameters and in the thermal properties of a device under the influence of surrounded devices biased.

Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O) devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are investigated. The I/O device degrades more than the Core device under the same stress electric field due to the different gate oxide processes in these two types of devices. Both the oxide trap charge and interface trap lead to the transfer characteristics degradations of the device after NBTI. While the near interfacial traps result in the increase of low frequency noise (LFN). The trap densities near the silicon/gate oxide interface introduced by stress are extracted using the LFN method. NBTI-induced gate current increase is observed for Core device, but not for I/O device. It is result from the enhanced tunneling process, which is induced by the increase of electric field in the gate oxide after charge trapping at or near the channel interface. The gate width and length dependences of NBTI are observed. The enhanced NBTI degradation observed in short channel and narrow channel device is result from the enhanced NBTI effect at channel edge regions. The larger hole concentration is a main cause of the more serious NBTI degradation at the channel edge regions, including the nearby region of STI sidewall along the channel width direction and the gate edge region along the channel length direction. This conclusion is also verified by the TCAD simulations.

Microcrystalline array structures induced by heat treatment of friction-transferred organic semiconductor films

The correlation between molecular orientation and optoelectrical properties is most critical to the future design of molecular materials. We made highly-anisotropic microcrystalline array structures with an organic semiconductor, a methoxy-substituted thiophene/phenylene co-oligomer (TPCO), by depositing it on friction-transferred poly(tetrafluoroethylene) (PTFE) layers fabricated on substrates with several heat treatments. Polarising microscope observation, polarised emission and absorption spectra measurements indicated that the TPCO molecules aligned along the drawing direction of PTFE. Using these films, we fabricated two types of field-effect transistors (FETs) and compared them with those using non-heated TPCO films which provide aligned pleats structures. Ones had the channel length direction parallel to the drawing direction of PTFE and the others had the channel length direction perpendicular to that drawing direction. As for the microcrystalline array films, the mobility ratio of the former FET to that of the latter device was about 27 in the saturation region, while the emission polarisation ratio was 4.5. The heat treatment promoted the crystal growth to enhance the mobility while retaining the high anisotropy. The results demonstrate that the heat treatments of the TPCO films on the friction-transferred layers were useful for controlling crystallinity and orientation of the molecules.

Reduced variability of drain-induced barrier lowering and subthreshold slope at high temperature in bulk and silicon-on-thin-buried-oxide (SOTB) MOSFETs

The temperature dependence of the variability of drain-induced barrier lowering (DIBL) and subthreshold slope (SS) is experimentally investigated in bulk and fully depleted silicon-on-thin-buried-oxide MOSFETs. Measurement results show that variability of both DIBL and SS is reduced at high temperature. The origins of these new findings are explained and confirmed by device simulations. It is found that reduced variability of DIBL at high temperature originates from randomness along the channel length direction (source–drain asymmetry), while reduced variability of SS at high temperature is mainly influenced by randomness along the channel width direction.

The effect of channel uniaxial strain on thermal conductivity of graphene nano-ribbon field effect transistor

The effect of channel uniaxial strain on thermal conductivity of graphene nano-ribbon field effect transistor (GNRFET) is analyzed by self-consistent Hückel method. The supposed strains are tensile and its values are 2% to 24% of lattice constant. All of the assumed strains are applied to the channel length direction. Energy band gap, density of states (DOS), phonon transmission, thermal conductivity, and I–V characteristics of the GNRFET have been calculated. The results show that by increasing the strain, the energy band gap of the channel is increased and the drain current is decreased. Also by increasing the band gap, phonon transmission is decreased. Maximum phonon transmission occurs in 8% strain. By considering all of these parameters, the results show that there is a maximum thermal conductivity versus temperature in 8% uniaxial strain that is more than the bare one and its value is decreased intensively in 16% and 24% strain. This is due to maximum phonon transmission that is observed in 8% strain and increasing the DOS around the energy band gap in this value. Also, it is observed that in the energy range of more than 0.75 eV, by increasing the strain, thermal conductivity is increased.

Ultrashort intrinsic-like channel FETs with nanodot-type floating gate utilizing biomaterial

We investigated the electrical characteristics of an n–i–n-type FET of a sub-10 nm channel with nanoparticles (NPs). To fabricate the FET, a V-groove was formed in a silicon-on-insulator substrate by anisotropic wet etching. Cage-shaped proteins (ferritin) was used for the formation and placement of NPs. A solution of ferritin containing a metal oxide core was dropped onto the substrate, and spin drying was performed to arrange the NPs at the bottom of the V-groove. NPs served as a floating gate for this device. Threshold voltage (Vth) shift was confirmed as a memory operation in devices with NPs. The Vth shift was clearly observed in different types of NPs. The Vth shift was controlled along the channel length direction by a single nanodot floating gate.

On the Bipolar DC Flow Field-Effect-Transistor for Multifunctional Sample Handing in Microfluidics: A Theoretical Analysis under the Debye⁻Huckel Limit.

We present herein a novel method of bipolar field-effect control on DC electroosmosis (DCEO) from a physical point of view, in the context of an intelligent and robust operation tool for stratified laminar streams in microscale systems. In this unique design of the DC flow field-effect-transistor (DC-FFET), a pair of face-to-face external gate terminals are imposed with opposite gate-voltage polarities. Diffuse-charge dynamics induces heteropolar Debye screening charge within the diffuse double layer adjacent to the face-to-face oppositely-polarized gates, respectively. A background electric field is applied across the source-drain terminal and forces the face-to-face counterionic charge of reversed polarities into induced-charge electroosmotic (ICEO) vortex flow in the lateral direction. The chaotic turbulence of the transverse ICEO whirlpool interacts actively with the conventional plug flow of DCEO, giving rise to twisted streamlines for simultaneous DCEO pumping and ICEO mixing of fluid samples along the channel length direction. A mathematical model in thin-layer approximation and the low-voltage limit is subsequently established to test the feasibility of the bipolar DC-FFET configuration in electrokinetic manipulation of fluids at the micrometer dimension. According to our simulation analysis, an integrated device design with two sets of side-by-side, but upside-down gate electrode pair exhibits outstanding performance in electroconvective pumping and mixing even without any externally-applied pressure difference. Moreover, a paradigm of a microdevice for fully electrokinetics-driven analyte treatment is established with an array of reversed bipolar gate-terminal pairs arranged on top of the dielectric membrane along the channel length direction, from which we can obtain almost a perfect liquid mixture by using a smaller magnitude of gate voltages for causing less detrimental effects at a small Dukhin number. Sustained by theoretical analysis, our physical demonstration on bipolar field-effect flow control for the microfluidic device of dual functionalities in simultaneous electroconvective pumping and mixing holds great potential in the development of fully-automated liquid-phase actuators in modern microfluidic systems.

전산유체해석을 이용한 열교환형 수증기 개질기의 디자인 파라미터 연구

In this study, CFD model for a Heat Exchange Steam Reformer (HESR) used for a 10kW SOFC system is developed for the design optimization of the HESR. The model is used to explore the effect of design parameters on the performance of the HESR. In the HESR, heat is delivered from the hot gas channel to the fuel channel to supply the heat required for the fuel reforming. In the fuel channel where the fuel is reformed, thermo-fluid dynamics, heat transfer, and chemical reaction are considered to predict the performance of the reformer. The model is validated with experimental data within 2~3% error. The validated model is used for the parametric study of the HESR design. Channel length, channel diameter, and flow direction are selected as the design parameters. The effects of the HESR design parameters on the outlet temperature, outlet H2 mole fraction, and pressure drop across the reformer are presented using the model.

Ultra-short channel junctionless transistor with a one-dimensional nanodot array floating gate

The electrical properties of a junctionless field-effect transistor with a sub-10-nm scale channel and FeOx nanoparticles (NPs) were studied. The anisotropic wet etching of a silicon-on-insulator substrate was used to form V-grooves and define the nanometer-scale channel. The NPs were selectively placed on the bottom of the V-groove using the bio-nano process. Low-voltage operation and a wide threshold voltage (Vth) shift as memory behavior were confirmed in a device with a 3.6-nm channel length. These results indicate that the Vth is controlled by the single-nanodot floating gate along the channel length direction.

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

In this paper, dc-stress-induced degradation in bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is systemically characterized and investigated. Compared with normal poly-Si TFTs, BG poly-Si TFTs exhibit better hot-carrier (HC) reliability, better self-heating (SH) reliability, and better negative bias temperature (NBT) instability. Resulting from the heavily doped BG lines inside the active channel, lateral electric field reduction at the drain side, Joule heat diffusion enhancement at the channel length direction, and boron-hydrogen bond formation at interface/grain boundaries are, respectively, responsible for the improved HC reliability, SH reliability, and NBT reliability in BG poly-Si TFTs. In addition, stress V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> -dependent HC degradation with fixed stress Vd, stress power density-dependent SH degradation, and vertical electrical field-dependent NBT degradation are also examined in both normal poly-Si TFTs and BG poly-Si TFTs. All test results indicate that such high-performance and highly reliable BG poly-Si TFT has a great potential for system-on-panel application.

High-Voltage LDMOS Transistor With Split-Gate Structure for Improved Electrical Performance

An n-channel split-gate laterally double-diffused metal-oxide-semiconductor (LDMOS) device is presented. The proposed split-gate LDMOS has a primary gate (PG) and floating gate (FG). The FG is formed by spacer etching and placed along the perimeter of the PG. The potential of the FG is determined by the potential of the PG and the capacitive coupling ratio. Therefore, the FG has lower potential than that of the PG. This potential difference along the channel length direction accelerates channel carriers, which ultimately enhances device performances. From device measurements, the fabricated splitgate LDMOS devices showed improved electrical characteristics: lower drain-induced barrier lowering; higher transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ); lower drain conductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 1/ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rout</sub> ); lower ON-resistances R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ; and higher early voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EA</sub> = I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> .

An embedded nonvolatile memory cell with spacer floating gate for power management integrated circuit applications

This paper describes a simple nonvolatile memory cell with a poly-Si spacer floating gate for power management integrated circuit applications. The proposed memory cell is fabricated using a 0.35μm double-poly high-voltage CMOS process which includes PIP capacitor, LV (5V), and HV (20V) CMOS devices. The floating gates of the proposed cell are buried under a LDD spacer oxide; thus the unit cell can be scaled easily in the channel length direction. In addition, any extra photo masking step is not required for the proposed cell in the applied fabrication process. The proposed cell shows an acceptable threshold voltage window of up to 104 cycles and less than 2% threshold voltage shifts in an 85°C retention test.

Channel Length Scaling and Surface Nitridation of Silicon Nanocrystals for High-Performance Electron Devices

Silicon nanocrystal (SiNC)-based thin-film devices have been fabricated, where the idea of scaling down of channel length was implemented in such a way that very few SiNCs can be fitted inside the channel in the channel length direction in order to decrease the number of barriers to increase electrical conductivity. In this study, we have demonstrated the scaling down of channel length to 20 nm in order to reduce the number of barriers provided by each of the SiNCs, which are fabricated using a very high-frequency (VHF) plasma-enhanced chemical vapor deposition (CVD) system with a diameter of 10±1 nm. A high electrical conductivity has been achieved by optimizing channel length. In addition, we have demonstrated the surface nitridation of SiNCs to protect the highly reactive surface of SiNCs from further natural oxidization and successfully suppressed the degradation of transport properties.

Effect of channel dopant uniformity on MOSFET threshold voltage variability

The effect of the dopant uniformity in an MOSFET channel on the threshold voltage variability is studied with a simple model and the test MOSFET array which includes many MOSFETs with different channel length and width. The simple model shows that the channel uniformity in channel length direction affects the threshold voltage variability. Takeuchi coefficient as a function of the channel length is calculated from the measured threshold voltage data. The electrical channel length as a function of the gate voltage is extracted using channel resistance method. It is found that those data show the similar degree of the channel dopant uniformity for MOSFETs having various channel structures.