Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

Chao Peng,Rui Gao,Yiqiang Chen,Zhifeng Lei,Yunfei En,Yun Huang,Zhangang Zhang

doi:10.1109/access.2020.2997463

Chao Peng, Rui Gao + Show 5 more

Open Access

https://doi.org/10.1109/access.2020.2997463

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Abstract

The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O) devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are investigated. The I/O device degrades more than the Core device under the same stress electric field due to the different gate oxide processes in these two types of devices. Both the oxide trap charge and interface trap lead to the transfer characteristics degradations of the device after NBTI. While the near interfacial traps result in the increase of low frequency noise (LFN). The trap densities near the silicon/gate oxide interface introduced by stress are extracted using the LFN method. NBTI-induced gate current increase is observed for Core device, but not for I/O device. It is result from the enhanced tunneling process, which is induced by the increase of electric field in the gate oxide after charge trapping at or near the channel interface. The gate width and length dependences of NBTI are observed. The enhanced NBTI degradation observed in short channel and narrow channel device is result from the enhanced NBTI effect at channel edge regions. The larger hole concentration is a main cause of the more serious NBTI degradation at the channel edge regions, including the nearby region of STI sidewall along the channel width direction and the gate edge region along the channel length direction. This conclusion is also verified by the TCAD simulations.

Highlights

Negative bias temperature instability (NBTI) is a major reliability concern for modern CMOS technologies [1]–[3]
Where q is the electron charge, Cox is the gate oxide capacitance per unit area, tox is the gate oxide thickness, εox is the permittivity of the oxide, Not and Nit are the densities of the stress-induced oxide trapped charge and interface traps in the gate oxide, respectively
Significant negative threshold voltage shifts and transconductance reductions are observed for Core pMOS after NBTI stress, which is result from the generation of trapped charges and interface traps in the gate oxide

Summary

INTRODUCTION

Negative bias temperature instability (NBTI) is a major reliability concern for modern CMOS technologies [1]–[3] It is mainly manifested as the threshold voltage shift, transconductance decrease, saturate current decrease and subthreshold swing increase of the pMOSFET due to the trap charge generated in the gate oxide. The nitride oxide or high-k gate dielectric introduced to reduce gate leakage current has worse hole trapping characteristics than the conventional SiO2 dielectric layer [6] These process variations may change the degradation mechanisms of NBTI. It is generally believed that NBTI is only related to the electric field perpendicular to the channel of MOSFETs, and does not depend on the transverse electric field along the channel direction [1] It should not exhibit the gate length and width dependence. Low frequency noise is proved to be sensitive to the NBTIinduced oxide traps and is an effective way to extract the trap state

EXPERIMENTAL DETAILS

RESULTS

DEGRADATION OF LOW-FREQUENCY CHARACTERISTIC

INFLUENCE OF GATE OXIDE PROCESS AND DEVICE DIMENSION ON NBTI EFFECTS

CONCLUSION