Quantitative Analysis of Channel Width Effects on Electrical Performance Degradation of Top-gate Self-aligned Coplanar IGZO Thin-film Transistors under Self-heating Stresses

Abstract

In this study, a quantitative analysis was conducted on the effects of channel width on electrical performance degradation induced by self-heating stress (SHS) in top-gate self-aligned coplanar indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). From the transfer and capacitance-voltage curves obtained before and after SHS, we revealed that the electrical performance of the TFT was nonuniformly degraded along the channel length direction and the degree of this degradation was more significant in TFTs with a wider channel width. The threshold voltage shift (ΔVSUBTH/SUB) under SHS in the fabricated IGZO TFT was mainly attributed to the increase in the density of shallow donor states and acceptor-like deep states in the IGZO active region and electron trapping into the fast and slow traps in the SiOSUBX/SUB gate dielectric. In addition, we conducted a decomposition of the SHS-induced ΔVSUBTH/SUB originated from each degradation mechanism using the subgap density of states-based ΔVSUBTH/SUB decomposition technique for TFTs with different channel widths. Although every ΔVSUBTH/SUB from each degradation mechanism increased as the channel width increased, increased electron trapping into the slow trap in the SiOSUBX/SUB gate dielectric was the dominant reason for the larger ΔVSUBTH/SUB under SHS in IGZO TFTs with a wider channel width.