Capacitor-less Low-dropout Regulator Research Articles

Fast-transient capacitor-less low-dropout regulator with input current-differencing and dynamic current-boosting

Transient response improvement of a capacitor-less low-dropout regulator with input current-differencing is presented in this paper. The Miller compensation technique with series resistance is used to establish the stability and reduce the on-chip capacitor. As a result, the on-chip compensation capacitor of the proposed LDO is reduced to 4 pF which makes it suitable for portable SoC applications. The dynamic current-boosting technique is simultaneously applied to both the input current and the gate of the pass transistor to improve the line and load transient responses of the proposed LDO. The output voltage is regulated at 1 V with a dropout voltage of about 100 mV. The proposed circuit is simulated in TSMC 0.18 μm CMOS technology and its quiescent current is 42 μA. The simulation results of both the line and load transient responses show considerable improvement in the over/undershoot and the settling time of the proposed LDO as well as better transient performance compared to the similar previous works. The output voltage over/undershoot amplitudes of the proposed LDO are obtained 46/100 mV with the settling time of less than 2 μs for the load current changes from 0.1 to 100 mA with 1 µs rise/fall times.

Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator

This paper presents a study by SPICE simulations and experimental data of a capacitor-less low-dropout (CL–LDO) voltage regulator (VR) by using a novel backend technique to improve its electrical performance. This study regards the use of an octagonal layout style in the pass device MOSFET of a CL–LDO VR to mainly boost its open-loop voltage gain and reduce output impedance. The results show that this innovative layout approach used in the CL–LDO voltage regulator can increase its power supply rejection ratio (PSRR) in approximately 2 dB (60 Hz), without degrading its quiescent current (Iq) (improvement of 2% better), and without wasting additional die area, in comparison to the one that its pass MOSFETs was implemented by using standard rectangular layout style. The 130 nm Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) manufacturing process from GlobalFoundries was used to implement both CL–LDO VRs, via MOSIS Educational Program. The die areas of each CL–LDO VRs are the same and equal to 0.00994mm2.

A Fast-Transient Output Capacitor-Less Low-Dropout Regulator Using Active-Feedback and Current-Reuse Feedforward Compensation

In this paper, output capacitor-less low-dropout (LDO) regulator using active-feedback and current-reuse feedforward compensation (AFCFC) is presented. The open-loop transfer function was obtained using small-signal modeling. The stability of the proposed LDO was analyzed using pole-zero plots, and it was confirmed by simulations that the stability was ensured under the load current of 50 mA. The proposed compensation method increases gain-bandwidth product (GBW) and reduces the on-chip compensation capacitor. The proposed AFCFC technique was applied to a three-stage output capacitor-less LDO. The LDO has a GBW of 5.6 MHz with a small on-chip capacitor of 2.6 pF. Fast-transient time of 450 ns with low quiescent current of 65.8 μA was achieved. The LDO was fabricated in 130 nm CMOS process consuming 180 × 140 μm2 of the silicon area.

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit * * Project supported by the National Natural Science Foundation of China (Nos. 61401137, 61404043, 61674049).

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE) circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA. The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV. Moreover, the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.

Fast‐transient high‐performance 0.18 μm CMOS LDO for battery‐powered systems

A low-power 0.18 µm CMOS capacitor-less low-dropout voltage regulator for battery-operated portable devices is presented. A high-gain telescopic cascode-compensated amplifier is used to attain a stable topology with good static performances, while a very simple dynamic biasing circuit significantly enhances transient performances with no quiescent current penalty. Post-layout results show a 1.8 V output voltage from a 3.6 to 1.9 V battery input voltage, delivering a 50 mA load current over a 100 pF load. The quiescent current is only 7 µA, the line and load regulations are, respectively, 0.039 mV/V and 0.17 mV/mA, and settling times are lower than 3.9 µs at full load transient.

A Low-Noise Output Capacitorless Low-Dropout Regulator With a Switched-RC Bandgap Reference

Low-noise linear regulators are critical for power supply regulation of noise-sensitive circuits, such as ADCs, phaselocked loops, and other mixed-signal/RF system-on-a-chip designs. A low-noise low-dropout (LN-LDO) regulator using switched-RC bandgap reference and a multiloop, unconditionally stable error amplifier for output capacitorless operation is presented in this paper. A sample-and-hold switched-RC filter is developed to reduce the noise of the bandgap reference and drain-side modulated current-mode chopping technique is proposed to reduce the flicker (1/f) noise of the error amplifier. A switched capacitor notch filter is utilized to filter out the residual chopping ripple of the error amplifier. Thermal noise of the current reference circuit which is significant at such low noise levels is also reduced by using a low-area penalty passive RC filter. These techniques reduce the total integrated output noise of the LDO in the 10 Hz to 100 kHz band from 95.3 μV RMS down to 14.8 μV RMS . The LDO delivers a maximum load current of 100 mA with a dropout voltage of 230 mV and a quiescent current consumption of 40 μA. It achieves a power supply rejection of 50 dB at 10 kHz for a programmable output voltage range of 1-3.3 V. Fabricated in a 0.25 μm CMOS process, the LDO core occupies an area of 0.18 mm 2 .

An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6[Formula: see text]V, dropout voltage of 200[Formula: see text]mV and a quiescent current of 64.4[Formula: see text][Formula: see text]A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95[Formula: see text]mV for a load current changes from 0[Formula: see text]mA to 100[Formula: see text]mA and an overshoot of 150.1[Formula: see text]mV for a current change of 100–0[Formula: see text]mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6[Formula: see text][Formula: see text]V/mA and power supply rejection (PSR) of [Formula: see text]47.8[Formula: see text]dB@ 10[Formula: see text]kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180[Formula: see text]nm UMC CMOS process is employed.

Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs

Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs

Analysis, Design, and Performance Evaluation of a Dynamically Slew Enhanced Adaptively Biased Capacitor-Less Low Dropout Regulator

Dynamically slew enhanced adaptive bias (DSE-AB) scheme has been recently introduced for an externally compensated (with-capacitor) regulator for achieving a very fast transient response. The combined effects of enhanced slew rate and expanded loop bandwidth using the DSE-AB scheme produce a very low undershoot and overshoot. When this scheme is directly applied to an internally compensated, capacitor-less low dropout regulator (CL-LDR) topology, besides the slew enhancement, the instantaneous dynamic current may reduce the damping factor momentarily and produce more ringing in the load transient response. This paper first analyzes the generation of momentary low damping factor in the CL-LDR that uses the DSE-AB scheme. A current limited DSE-AB scheme is also proposed to increase the momentary damping factor for minimizing the ringing in the settling behavior. To validate the proposed scheme, the CL-LDR is implemented in a 0.18 $ \mu$ m CMOS technology and the regulator's performance is evaluated in different dynamic conditions. Experimental result shows an undershoot of 45 mV during 0–100-mA load step and an overshoot of 25 mV during the other edge.

A capacitorless low-dropout regulator with enhanced slew rate and 4.5- $$\upmu \hbox {A}$$ μ A quiescent current

In this paper, an output-capacitorless, low-dropout (LDO) voltage regulator with excellent load regulation and fast recovery time was designed using two amplifiers, which provided high gain, high b...

Low Power Dropout Regulators with Efficiently Controlled Transient Response

Low-Dropout voltage regulators are significant part of VLSI design integrated chips and are used to provide steady supply voltage to noise sensitive analog/RF circuit blocks. It belongs to class of linear regulators designed to minimize the saturation of output pass transistor and its drive requirements. A capacitor-less low-dropout regulator with improved performance push-pull power transistor is described in the paper. The proposed LDO is stable over a wide range of load current and implemented in 65-nm CMOS process technology. The simulation illustrates that the regulator is able to convert VIN of 0.65V- 1.5V to output voltage of 0.5V. This LDO achieves power supply rejection of >40dB at 1 kHz operating frequency. It consumes a quiescent current less than 10 uA. It is capable of delivering a maximum load current of 70 mA with a dropout voltage of less than 220 mV. Keywordsdropout, regulators, low quiescent current, enhanced, capacitor-less.

Improved Transient Response Capacitor-less Low Drop-out (LDO) Regulator using Current Mode Transconductance Amplifier and Slew Rate Enhancement Technique

paper presents a capacitor-less low drop-out (LDO) regulator with current mode transconductance amplifier & slew-rate enhancement circuit. The proposed current mode transconductance amplifier as error amplifier improves the slew rate & slew- rate enhancement circuit further senses the transient voltage at the output of the LDO to increase the bias current of the error amplifier for a short duration. Hence, transient response of LDO has been further improved using these techniques. The proposed LDO regulator will be designed and simulated in 180nm CMOS technology.

High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator (LDO) for Mobile Applications Utilizing Frequency Response of Multiple Feedback Loops

This paper presents a novel capacitor-less low-dropout regulator (LDO) for mobile applications. The proposed capacitor-less LDO utilizes multiple feedback loops to satisfy several design challenges for some mobile applications which were not considered in the previous capacitor-less LDOs. The proposed LDO has a wide bandwidth of 3.03 MHz at a load current of 150 mA with a bias current of 40 $\mu\mbox{A}$ , and the best line and load regulations of 0.0024%/V and 0.0000417%/mA, respectively, which are improvements over previously reported LDOs. This chip has a 100 mV dropout voltage with a 150 mA maximum load current. A total capacitance of 29 pF was used with a chip size of 0.279 $\mbox{mm}^{2}$ .

Tradeoffs Aware Design Procedure for an Adaptively Biased Capacitorless Low Dropout Regulator Using Nested Miller Compensation

An adaptively biased, low dropout regulator (AB-LDR) that uses the nested Miller type frequency compensation has been explored in the literature for system-on-chip applications. However, those are mostly focused to solve only specific issues without accounting for all the design tradeoffs. Due to this, additional components/circuits are needed to mitigate the issues like $Q$ -peaking and poor dynamic response in capacitorless condition. In this paper, the various design tradeoffs particularly relevant to the nested Miller compensated regulator architecture, are clearly brought out. Then a detailed design procedure for the same architecture is proposed to achieve a low quiescent current, wide dynamic range, desired dynamic response and a high current efficiency over a given load range. An AB-LDR has been implemented in standard 0.18- $\mu$ m CMOS technology to validate the effectiveness of the proposed approach. Experimental results show a very good agreement with the theoretical analysis.

Design of low-power, fast-transient-response, capacitor-less low-dropout regulator for mobile applications

Design of low-power, fast-transient-response, capacitor-less low-dropout regulator for mobile applications

A 100-MHz Breakdown-Resilient Power Converter With Fully Monolithic Implementation on Nanoscale CMOS Process

A monolithic switched-capacitor power converter is designed in the nanoscale CMOS technology, employing a two-stage system architecture to mitigate overvoltage breakdown risk. The efficiency impact of various parasitic components is analyzed for design optimization on both the topology level and the device level. An external capacitorless low-dropout regulator with a wide bandwidth and a high power supply rejection ratio is introduced, removing high-frequency ripples and enabling a fast load transient response. The proposed design was implemented with the 180-nm CMOS process. At a switching frequency of 100 MHz, it regulates $V_\mathrm{out} $ at 0.8 V, with a maximum power efficiency of 60%. When the load current switches between 1.5 and 15 mA, $V_\mathrm{out} $ responds within 45 ns, with a voltage droop below 45 mV.

An Inductive Power and Data Telemetry Subsystem With Fast Transient Low Dropout Regulator for Biomedical Implants.

This paper presents a capacitorless low-dropout (LDO) regulator with fast transient response and data reverse telemetry circuit for fully implantable wireless transmission applications. We propose a novel hybrid feedback structure using high-frequency compensation technology to achieve a rapid transient response for the LDO regulator. To reduce the size of the implant and transmit neural recordings through the same coil without interfering with power transmission, the load-shift-key (LSK) modulation technique is adopted for back data telemetry. The proposed implantable chip, fabricated using commercial 0.18 μm complementary metal oxide semiconductor technology, yielded an output power of 15 mW. Under 1.15 V operation voltage, the maximum overshoot and undershoot voltages were less than 45 mV and 55 mV, respectively, for a 15 mA full-load current whose rising and falling time were less than 100 ns. The proposed LSK transceiver uses a digitized demodulator to improve bandwidth efficiency for low carrier frequency operation.

A capacitor-less LDO regulator with dynamic transconductance enhancement technique

A current-efficient, capacitor-less low-dropout regulator (LDO) with fast-transient response for portable applications is presented in this paper. It makes use of an adaptively biased common-gate amplifier to extend loop bandwidth of the LDO at heavy loads. Moreover, a dynamic transconductance enhancement circuit based on capacitive coupling detects rapid voltage spikes at the output, providing an extra large current to charge or discharge the gate capacitance of power transistor momentarily during transient. The proposed circuit has been implemented in a 0.35 µm standard CMOS process. Experimental results show that this fully-integrated LDO can deliver 100 mA load current at 200 mV dropout voltage. It only consumes 15 μA quiescent current and is able to recover within 1 µs under the maximum load current change, with undershoot/overshoot voltages controlled below 250 mV. Loop stability is kept well at light loads (Iload = 100 μA) even when a 100 pF output-parasitic capacitor is applied.

A Capacitor-less Low Dropout Regulator for Enhanced Power Supply Rejection

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

In recent years, radio frequency (RF) energy harvesting systems have gained significant interest as inexhaustible replacements for traditional batteries in RF identification and wireless sensor network nodes. This paper presents an ultra-low-power integrated RF energy harvesting circuit in a SMIC 65-nm standard CMOS process. The presented circuit mainly consists of an impedance-matching network, a 10-stage rectifier with order-2 threshold compensation and an ultra-low-power power manager unit (PMU). The PMU consists of a voltage sensor, a voltage limiter and a capacitor-less low-dropout regulator. In the charge mode, the power consumption of the proposed energy harvesting circuit is only 97 nA, and the RF input power can be as low as $$-$$-21.4 dBm $$(7.24\,\upmu \hbox {W})$$(7.24μW). In the burst mode, the device can supply a 1.0-V DC output voltage with a maximum 10-mA load current. The simulated results demonstrate that the modified RF rectifier can obtain a maximum efficiency of 12 % with a 915-MHz RF input. The circuit can operate over a temperature range from $$-40\hbox { to }125\,^{\circ }\hbox {C}$$-40to125?C which exceeds the achievable temperature performance of previous RF energy harvesters in standard CMOS process.