Abstract
This paper presents a study by SPICE simulations and experimental data of a capacitor-less low-dropout (CL–LDO) voltage regulator (VR) by using a novel backend technique to improve its electrical performance. This study regards the use of an octagonal layout style in the pass device MOSFET of a CL–LDO VR to mainly boost its open-loop voltage gain and reduce output impedance. The results show that this innovative layout approach used in the CL–LDO voltage regulator can increase its power supply rejection ratio (PSRR) in approximately 2 dB (60 Hz), without degrading its quiescent current (Iq) (improvement of 2% better), and without wasting additional die area, in comparison to the one that its pass MOSFETs was implemented by using standard rectangular layout style. The 130 nm Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) manufacturing process from GlobalFoundries was used to implement both CL–LDO VRs, via MOSIS Educational Program. The die areas of each CL–LDO VRs are the same and equal to 0.00994mm2.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
