An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

Abstract

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6[Formula: see text]V, dropout voltage of 200[Formula: see text]mV and a quiescent current of 64.4[Formula: see text][Formula: see text]A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95[Formula: see text]mV for a load current changes from 0[Formula: see text]mA to 100[Formula: see text]mA and an overshoot of 150.1[Formula: see text]mV for a current change of 100–0[Formula: see text]mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6[Formula: see text][Formula: see text]V/mA and power supply rejection (PSR) of [Formula: see text]47.8[Formula: see text]dB@ 10[Formula: see text]kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180[Formula: see text]nm UMC CMOS process is employed.