Capacitor-less Low-dropout Regulator Research Articles

회로 최적화를 위한 외부 커패시터가 없는 LDO 레귤레이터의 안정도와 PSR 성능 모델

한정된 배터리 용량으로 장시간 모바일 시스템을 구동시키기 위하여 저전력 설계에 대한 요구가 높아지면서 PMIC(Power Management IC)의 핵심 부분인 LDO(Low Drop-Out) 레귤레이터의 설계에 대한 관심이 증가하고 있다. 본 논문에서는 Dongbu HiTek <TEX>$0.5{\mu}m$</TEX> BCDMOS 공정을 이용하여 최적화 기법 중 하나인 기하 프로그래밍(Geometric Programming: GP)을 통해 외부 커패시터가 없는 LDO 레귤레이터의 성능을 최적화하였다. 계수가 양수인 단항식 (monomial)으로 모델링된 트랜지스터의 특성 파라미터들을 이용하여 안정도(stability)와 PSR(Power-Supply Rejection)과 같은 LDO 레귤레이터의 특성을 기하 프로그래밍(Geometric Programming: GP)에 적용 가능한 형태로 유도하였다. 위상 마진(phase margin)과 PSR 모델은 시뮬레이션 결과와 비교하였을 때 각각 평균 9.3 %와 13.1 %의 오차를 보였다. 제안한 모델을 사용하여 PSR 제약 조건이 바뀔 경우, 자동화된 회로 설계를 수행하였고, 모델의 정확도를 검증하였다. 본 논문에서 유도된 안정도와 PSR 모델을 이용하면 회로의 목표 성능이 변화하더라도 부가적인 설계 시간을 줄이면서 목표 성능을 가진 회로를 재설계하는 것이 가능할 것이다. LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek <TEX>$0.5{\mu}m$</TEX> BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.

A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load

A Weighted Current Feedback (WCF) technique for output capacitorless low-dropout (OCL-LDO) regulator is presented in this paper. Through feedback of a weighted current, the WCF permits smart management of the output impedance as well as the gain from the inter-gain stage. Based on the Routh-Hurwitz stability criterion, the WCF can avoid the right-half plane (RHP) pole and push the left-half plane (LHP) non-dominant complex pole pair to a higher frequency. Besides, it provides good regulator loop gain and fast transient response. Validated by UMC 65 nm CMOS process, the simulation and measurement results have shown that the WCF LDO regulator can operate at a load capacitance (C L ) range from 470 pF to 10 nF with only 3.8 pF compensation capacitor. At a supply of 0.75 V and a quiescent current of 15.9 μA, the proposed circuit can support a maximum load current (I L ) of 50 mA. When I L switches from 0 to 50 mA in 100 ns, the output can settle within 400 ns for the whole C L range. For a case of single capacitor (C L 470 pF), the settling time is only 250 ns. The comparison results have shown that the WCF LDO regulator offers a comparable or better transient figure-of-merit (FOM) and additional merit to drive wide load capacitance range.

A FVF LDO Regulator With Dual-Summed Miller Frequency Compensation for Wide Load Capacitance Range Applications

This paper presents a proposed Flipped Voltage Follower (FVF) based output capacitorless low-dropout (OCL-LDO) regulator using Dual-Summed Miller Frequency Compensation (DSMFC) technique. Validated by UMC 65-nm CMOS process, the simulation results have shown that the proposed LDO regulator can be stabilized by a total compensation capacitance (CC) of 8 pF for a load capacitance (CL) ranging from 10 pF to 10 nF. It consumes 23.7 μA quiescent current with a 1.2 V supply voltage. With a dropout voltage of 200 mV, the LDO regulator can support a maximum 50 mA load current. It can settle in less than 1.7 μs with a 1% accuracy for the whole CL range. The proposed LDO regulator is comparable to other reported works in terms of figure-of-merit (FOM). Most significantly, it can drive the widest range of CL and achieve the highest CL(max)/CC ratio with respect to the counterparts.

Transient Response Enhancement with Fast Transient Controller for Capacitor-Less LDO Regulator

This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.

External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range

This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed. The PSR performance is improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. The effectiveness of the PSR enhancement technique is experimentally verified with an LDO that was fabricated in a 0.18 µm CMOS technology with a power supply of 1.8 V. The active core chip area is 0.14 mm², and the entire proposed LDO consumes 80 µA of quiescent current during operation mode and 55 µA of quiescent current in standby mode. It has a drop-out voltage of 200 mV when delivering 50 mA to the load. The measured PSR is better than –56 dB up to 4 MHz when delivering a current of 50 mA. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively.

An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control

This brief presents a current-efficient fully integrated low-dropout regulator (LDO) for system-on-a-chip applications. A common-gate error amplifier with high bandwidth and slew rate is proposed to reduce the output voltage spike and the response time of the LDO greatly. In addition, the loop employs a direct dynamic charging technique to enhance load-transient responses by directly detecting voltage variations through a capacitive coupling high-pass filter. The circuit has been implemented in a 0.35-μm standard complementary metal-oxide-semiconductor process and occupies an active chip area of 0.064 mm2. Experimental results show that it can deliver a load current of 100 mA at a dropout voltage of 150 mV. It only consumes a quiescent current of 7 μA at light loads and can recover within 0.15 μs, even under the maximum load current change. Consequently, a faster and more accurate capacitorless LDO can be achieved.

An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18µm CMOS

SUMMARY This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 μm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closedloop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/ √ Hz, current consumption of 14 μA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter’s building block for low power design. The filter’s single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signalto-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 μW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 μm CMOS process.

Capacitor-less low-dropout regulator with slew-rate-enhanced circuit

A capacitor-less low-power low-dropout regulator (LDR) with a slew-rate-enhanced circuit (SRE) was proposed. The SRE uses six transistors to constitute two comparators and two auxiliary transistors. The comparators sense the variation of load current to control one of the auxiliary transistors that generate a large current to charge or discharge the gate capacitor of the power transistor; thus SRE increases the slew-rate at the gate of the power transistor. The quiescent current of the LDR remains 18 A at the steady state because the auxiliary transistors work at the cut-off region to reduce power consumption. When load current changes between 0.1 and 100 mA, the variation of the output voltage of the LDR is improved from 675 to 300 mV.