Abstract
An adaptively biased, low dropout regulator (AB-LDR) that uses the nested Miller type frequency compensation has been explored in the literature for system-on-chip applications. However, those are mostly focused to solve only specific issues without accounting for all the design tradeoffs. Due to this, additional components/circuits are needed to mitigate the issues like $Q$ -peaking and poor dynamic response in capacitorless condition. In this paper, the various design tradeoffs particularly relevant to the nested Miller compensated regulator architecture, are clearly brought out. Then a detailed design procedure for the same architecture is proposed to achieve a low quiescent current, wide dynamic range, desired dynamic response and a high current efficiency over a given load range. An AB-LDR has been implemented in standard 0.18- $\mu$ m CMOS technology to validate the effectiveness of the proposed approach. Experimental results show a very good agreement with the theoretical analysis.
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