Abstract
In this paper, a capacitor-less flipped voltage follower (FVF) low dropout (LDO) regulator using nested miller compensation with a large feed-forward transconductor (NMCLFT) is presented. The LDO regulator is a dual-summing based three-stage high-gain structure and NMCLFT stabilizes the feedback loop for the load current ranges of 0 to 50 mA with load capacitances of 0 to 100 pF. This LDO regulator uses the multiple feed-forward paths which enhance the unity gain bandwidth (UGB) as well as the transient responses. The large feed-forward transconductor separates the non-dominant complex poles of nested miller compensation (NMC) into two simple poles and pushes one of the poles into high-frequency. It also provides a strong low-frequency left-half plane (LHP) zero and pushes right-half plane (RHP) zero of NMC into high-frequency and makes the multi-pole LDO regulator into a single-pole LDO for all the cases, from light load to heavy load with different load capacitor corners. The NMCLFT eliminates the minimum load current and minimum load capacitance constraints with improved transient response. The proposed LDO regulator achieves the settling time of 120 ns with the minimum edge time of 10 ns for the load current ranges of 0 to 50 mA and the load capacitance ranges of 0 to 100 pF. This LDO is implemented in 130 nm CMOS technology and it consumes a quiescent current of 63μA.
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