A 90nm CMOS «LDO» regulator with high load regulation using a gain boost-up technique

Abstract

In this paper, a new type of a 90nm CMOS LDO regulator with high load regulation using a gain goost-up technique. The development of low drop-out (LDO) regulator architectures in the power management family is necessary to reduce the standby power of portable applications such as cellular phones and PDAs. In essence, this LDO regulator suffers from an inherent load regulation which impedes to work under various applications. Indeed, this paper discusses a technique that enables the practical realizations of high Load regulation LDO's at low voltages. The objective of this research is to develop novel LDO regulators that can achieve a high precision of LDO which requires a high loop gain performance. Moreover, one of the performances which is enhanced by the augmentation of dc open loop gain is the load regulation. The LDO is implemented in 90 nm CMOS technology and achieves a power-supply rejection ratio better than −70 dB up to 100 KHz for load currents up to 100 mA. The voltage regulator provides maximum 110 mA current, moreover with a 1.2V supply voltage, thus this LDO regulator providing an output of 1 V with a 200mV drop-out voltage.